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TDA9983B
HDMI transmitter up to 150 MHz pixel rate with 3 x 8-bit video inputs and 4 x I2S-bus with S/PDIF
Rev. 01 -- 20 May 2008 Product data sheet
1. General description
The TDA9983B is an HDMI transmitter (which also supports DVI) that enables a 3 x 8-bit RGB or YCBCR video stream (with a pixel rate up to 150 MHz for the TDA9983BHW/15 version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and the additional information required by all the HDMI 1.2a standards. A programmable upscaling block enables a 720p/1080i output from a standard definition input. An intrafield deinterlacer is included in the scaler. In order to be compatible with most applications, the TDA9983B integrates a full programmable input formatter and color space conversion block. The video input formats accepted are YCBCR 4 : 4 : 4 (up to 3 x 8-bit), YCBCR 4 : 2 : 2 semi-planar (up to 2 x 12-bit), YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 x 12-bit). For ITU656-like formats, double edges are supported so that data can be sampled on rising and falling edges. The device can be controlled via an I2C-bus interface.
2. Features
I 3 x 8-bit video data input bus, CMOS and LV-TTL compatible I Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or VREF, HREF and FREF could be used for input data synchronization I Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus) I The TDA9983B has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio sampling rate up to 192 kHz I 250 MHz to 1.50 GHz HDMI transmitter operation I Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats I Programmable color space converter: N RGB to YCBCR N YCBCR to RGB I The upscaler enables a 720p/1080i output from a standard definition input using intelligent edge interpolation I Controllable via I2C-bus I Low power dissipation I 1.8 V and 3.3 V power supplies I Power-down mode
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
I Hard reset
3. Applications
I I I I I I I I I DVD players and recorders Set-Top Box (STB) AV receivers and amplifiers (repeater) Camcorders Digital still cameras Media players PVRs Media centers PCs, graphics add-in boards, notebook PCs Switches
4. Quick reference data
Table 1. Quick reference data VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol VDDA(FRO_3V3) VDDA(PLL_3V3) VDDD(3V3) VDDH(3V3) VDDC(1V8) Tamb fclk(max) Pcons Ptot Ppd Parameter free running oscillator 3.3 V analog supply voltage PLL 3.3 V analog supply voltage digital supply voltage (3.3 V) HDMI supply voltage (3.3 V) core supply voltage (1.8 V) ambient temperature maximum clock frequency power consumption worst case total power dissipation worst case power dissipation in power-down mode
[2] [2] [3] [2] [3] [1] [1]
Conditions
Min 3.0 3.0 3.0 3.0 1.65 0 81 -
Typ 3.3 3.3 3.3 3.3 1.8 322 338 458 472 13.5
Max 3.6 3.6 3.6 3.6 1.95 70 503 651 38.4
Unit V V V V V C MHz mW mW mW mW mW
TDA9983BHW/8 and TDA9983BHW/15
TDA9983BHW/8; up to 81 MHz
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
2 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 1. Quick reference data ...continued VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol fclk(max) Pcons Ptot Ppd Parameter maximum clock frequency power consumption total power dissipation power dissipation in power-down mode Conditions
[4] [4] [4]
Min 150 -
Typ 361 495 13.5
Max 583 732 38.4
Unit MHz mW mW mW
TDA9983BHW/15; up to 150 MHz
[1] [2]
The VDDD(3V3) and VDDC(1V8) power supplies must always follow the sequence shown in Figure 14 to ensure proper power-up conditions. Video format: a) Input 480p (ITU656 embedded sync, rising edge) b) Output 1080i (YCBCR 4 : 2 : 2) Worst case video format: a) Input 480p (YCBCR 4 : 2 : 2 semi-planar) b) Output 720p (YCBCR 4 : 2 : 2) Video format: a) Input 1080p (RGB 4 : 4 : 4 external sync, rising edge) b) Output 1080p (RGB 4 : 4 : 4)
[3]
[4]
5. Ordering information
Table 2. Ordering information Package Name TDA9983BHW HTQFP80 Description plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad Version SOT841-4 Type number
5.1 Ordering options
Table 3. Survey of type numbers Sampling frequency (Msample/s) 81 150 Application customer specific version customer specific version Extended type number TDA9983BHW/8/C1 TDA9983BHW/15/C1
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
3 of 119
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Product data sheet Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved. TDA9983B_1
6. Block diagram
NXP Semiconductors
VPP RST_N 42 3
VDDC(1V8) VDDD(3V3)
VDDH(3V3) VDDA(PLL_3V3) 28, 34 38 I2C_SCL 43 I2C_SDA 44 A0 41 A1 40 20 DDC_SCL DDC_SDA
VDDA(FRO_3V3)
13, 48, 16, 45, 23 71 59, 74
HPD
18
HPD MANAGEMENT
HARD RESET
I2C-BUS SLAVE
DDC-BUS
19
AP7 to AP0 ACLK
4 to 11 12 AUDIO PROCESSING DATA ISLAND PACKET IRQ GENERATION
17
INT
INFORMATION FRAMES AND PACKETS 68 to 70, 75 to 79 57 and 58, 61 to 65, 67 49 to 56 2 1 80 66 VIDEO INPUT PROCESSOR
27 26 30 VIDEO PROCESSING RGB YCBCR 4 : 4 : 4 3 x 8-bit COLOR SPACE CONVERTER RGB TO YUV YUV TO RGB (4 : 4 : 4)(1) DOWNSAMPLING FROM 4:4:4 TO 4 : 2 : 2(1) HDMI SERIALIZER 29 33 32 36 35
TXC+ TXC- TX0+ TX0- TX1+ TX1- TX2+ TX2-
VPA[7:0]
VPB[7:0] VPC[7:0] VSYNC/VREF HSYNC/HREF DE/FREF VCLK
UPSCALER(1) DEINTERLACER INTRAFIELD(1)
UPSAMPLING FROM 4:2:2 TO 4 : 4 : 4(1)
YCBCR 4 : 2 : 2 ITU656 or ITU656-like 14, 47, 72 VSSD
2 x 12-bit or 1 x 12-bit 15, 60, 73 VSSC 25, 31, 37 VSSH
TDA9983B
150 MHz pixel rate HDMI transmitter
22 VSSA(FRO_3V3)
39 VSSA(PLL_3V3)
46 VSSA(PLL_1V8)
21 TM
24 EXT_SWING
001aag248
TDA9983B
4 of 119
(1) Block can be bypassed.
Fig 1.
Block diagram
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
7. Pinning information
7.1 Pinning
74 VDDC(1V8) 71 VDDD(3V3) 80 DE/FREF
79 VPA[0]
78 VPA[1]
77 VPA[2]
76 VPA[3]
75 VPA[4]
70 VPA[5]
69 VPA[6]
68 VPA[7]
67 VPB[0]
65 VPB[1]
64 VPB[2]
63 VPB[3]
62 VPB[4]
HSYNC/HREF VSYNC/VREF VPP AP7 AP6 AP5 AP4 AP3 AP2
1 2 3 4 5 6 7 8 9
66 VCLK
73 VSSC
72 VSSD
61 VPB[5] 60 VSSC 59 VDDC(1V8) 58 VPB[6] 57 VPB[7] 56 VPC[0] 55 VPC[1] 54 VPC[2] 53 VPC[3] 52 VPC[4] 51 VPC[5] 50 VPC[6] 49 VPC[7] 48 VDDD(3V3) 47 VSSD 46 VSSA(PLL_1V8) 45 VDDC(1V8) 44 I2C_SDA 43 I2C_SCL 42 RST_N 41 A0 A1 40
001aag249
AP1 10 AP0 11 ACLK 12 VDDD(3V3) 13 VSSD 14 VSSC 15 VDDC(1V8) 16 INT 17 HPD 18 DDC_SDA 19 DDC_SCL 20 TM 21 VSSA(FRO_3V3) 22 VDDA(FRO_3V3) 23 EXT_SWING 24 VSSH 25 TXC- 26 TXC+ 27 VDDH(3V3) 28
TDA9983B
TX0- 29
TX0+ 30
VSSH 31
TX1- 32
TX1+ 33
VDDH(3V3) 34
TX2- 35
TX2+ 36
VSSH 37
VDDA(PLL_3V3) 38
Fig 2.
Pin configuration
7.2 Pin description
Table 4. Symbol HSYNC/HREF VSYNC/VREF VPP AP7 AP6 AP5
TDA9983B_1
Pin description Pin 1 2 3 4 5 6 Type[1] Description I I P I I I horizontal synchronization or reference input vertical synchronization or reference input programming voltage (must be connected to the ground of the digital core in normal operation) audio port 7 input; auxiliary (AUX) audio port 6 input; S/PDIF stream audio port 5 input; optional master clock MCLK for S/PDIF
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
VSSA(PLL_3V3) 39
5 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Pin description ...continued Pin 7 8 9 10 11 12 13 14 15 16 17 Type[1] Description I I I I I I P G G P O audio port 4 input; I2S-bus 3 audio port 3 input; I2S-bus 2 audio port 2 input; I2S-bus 1 audio port 1 input; I2S-bus 0 audio port 0 input; word select WS for I2S-bus audio clock input; clock SCK for I2S-bus supply voltage for input ports (3.3 V) ground for input ports ground for digital core supply voltage for digital core (1.8 V) interrupt output (open drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 V tolerant hot plug detect input; 5 V tolerant DDC-bus data input/output (open drain); must be connected to a pull-up resistor; 5 V tolerant DDC-bus clock output (open drain); must be connected to a pull-up resistor; 5 V tolerant internal test mode input (must be connected to the ground of the digital core in normal operation) analog ground for free running oscillator analog supply voltage for free running oscillator (3.3 V) external swing adjust input; a fixed resistor must be connected between this pin and VDDH(3V3) to set the HDMI output swing (see Section 8.14.1) ground for HDMI transmitter negative clock channel for HDMI output positive clock channel for HDMI output supply voltage for HDMI transmitter (3.3 V) negative data channel 0 for HDMI output positive data channel 0 for HDMI output ground for HDMI transmitter negative data channel 1 for HDMI output positive data channel 1 for HDMI output supply voltage for HDMI transmitter (3.3 V) negative data channel 2 for HDMI output positive data channel 2 for HDMI output ground for HDMI transmitter analog supply voltage for PLL (3.3 V) analog ground reference for PLL I2C-bus slave address input 1; bit 1 I2C-bus slave address input 0; bit 0 hard reset input; active LOW
(c) NXP B.V. 2008. All rights reserved.
Table 4. Symbol AP4 AP3 AP2 AP1 AP0 ACLK VDDD(3V3) VSSD VSSC VDDC(1V8) INT
HPD DDC_SDA DDC_SCL TM VSSA(FRO_3V3) VDDA(FRO_3V3) EXT_SWING
18 19 20 21 22 23 24
I I/O O I G P I
VSSH TXC- TXC+ VDDH(3V3) TX0- TX0+ VSSH TX1- TX1+ VDDH(3V3) TX2- TX2+ VSSH VDDA(PLL_3V3) VSSA(PLL_3V3) A1 A0 RST_N
TDA9983B_1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
G O O P O O G O O P O O G P G I I I
Product data sheet
Rev. 01 -- 20 May 2008
6 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Pin description ...continued Pin 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Type[1] Description I I/O P G G P I I I I I I I I I I P G I I I I I I I I I I P G G P I I I I I I I2C-bus clock input of device (open drain); must be connected to a pull-up resistor; 5 V tolerant I2C-bus data input/output of device; open drain; must be connected to a pull-up resistor; 5 V tolerant supply voltage for digital core (1.8 V) analog ground reference for PLL ground for input ports supply voltage for input ports (3.3 V) video port C input bit 7 video port C input bit 6 video port C input bit 5 video port C input bit 4 video port C input bit 3 video port C input bit 2 video port C input bit 1 video port C input bit 0 video port B input bit 7 video port B input bit 6 supply voltage for digital core (1.8 V) ground for digital core video port B input bit 5 video port B input bit 4 video port B input bit 3 video port B input bit 2 video port B input bit 1 video pixel clock input video port B input bit 0 video port A input bit 7 video port A input bit 6 video port A input bit 5 supply voltage for input ports (3.3 V) ground for input ports ground for digital core supply voltage for digital core (1.8 V) video port A input bit 4 video port A input bit 3 video port A input bit 2 video port A input bit 1 video port A input bit 0 video data enable input or field reference input exposed die pad; must be connected to the ground of the HDMI transmitter (VSSH)
(c) NXP B.V. 2008. All rights reserved.
Table 4. Symbol I2C_SCL I2C_SDA VDDC(1V8)
VSSA(PLL_1V8) VSSD VDDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] VDDC(1V8) VSSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] VDDD(3V3) VSSD VSSC VDDC(1V8) VPA[4] VPA[3] VPA[2] VPA[1] VPA[0] DE/FREF
Exposed die pad central G
TDA9983B_1
Product data sheet
Rev. 01 -- 20 May 2008
7 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
[1]
P = power supply; G = ground; I = input; O = output.
8. Functional description
The TDA9983B is designed to convert digital data (video and audio) into an HDMI or a DVI stream. This HDMI stream can handle RGB, YCBCR 4 : 4 : 4 and YCBCR 4 : 2 : 2. The TDA9983B can accept at its inputs any of the following video modes:
* * * *
RGB YCBCR 4 : 4 : 4 YCBCR 4 : 2 : 2 semi-planar YCBCR 4 : 2 : 2 ITU656 and ITU656-like
It can also handle audio. The TDA9983B can accept at its inputs any of the following audio buses:
* I2S-bus (4 lines): up to 8 audio channels * S/PDIF (1 channel): L-PCM (IEC 60958) or compressed audio (IEC 61937) 8.1 System clock
The clock management is based on a set of 3 PLLs that generate the different clocks required inside the chip. This includes:
* PLL double edge can generate a clock at twice the VCLK input frequency to capture
the data at the video input formatter
* PLL scaling can create a new video processing scaled clock taking into account the
scaling ratio programmed in the scaler
* PLL serializer is a system clock generator, which enables the stream produced by the
encoder to be transmitted on the HDMI data channel at ten times the sampling rate or more; see Section 8.14.2
8.2 Video input processor
The TDA9983B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0]. The TDA9983B can reallocate and swap each of the 3 ports input channels by inverting the bus and swapping each port. The TDA9983B can be set to latch data at either the rising or falling edge or both. The video input formats accept (see Table 5):
* * * *
RGB YCBCR 4 : 4 : 4 (up to 3 x 8-bit) YCBCR 4 : 2 : 2 semi-planar (up to 2 x 12-bit) YCBCR 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 x 12-bit)
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
8 of 119
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Product data sheet Rev. 01 -- 20 May 2008 [1]
(c) NXP B.V. 2008. All rights reserved. TDA9983B_1
NXP Semiconductors
Table 5. Color space RGB
Inputs of video input formatter Format Channels Sync Rising edge X X X X X X X X X X X X X X X X X X SMPTE293M SMPTE293M ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like Falling edge Double edge[1] Transmission input format Max. pixel clock on pin VCLK (MHz) 150 150 150 150 150 150 150 150 54.054 54.054 27.027 54.054 54.054 27.027 148.5 148.5 148.5 148.5 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 1080p 1080p 1080p 1080p Table 13 Table 11 Table 12 Table 9 Table 10 Table 8 Table 7 Max. input format Reference
4:4:4
3 x 8-bit
external external embedded embedded
Table 6
YCBCR
4:4:4
3 x 8-bit
external external embedded embedded
YCBCR
4:2:2
up to 1 x 12-bit ITU656-like
external external external embedded embedded embedded
up to 2 x 12-bit semi-planar
external external embedded embedded
150 MHz pixel rate HDMI transmitter
Double edge means both rising and falling edges.
TDA9983B
9 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 6. RGB 4 : 4 : 4 mappings RGB 4 : 4 : 4 (3 x 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] RGB 4 : 4 : 4 B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] RGB 4 : 4 : 4 G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] RGB 4 : 4 : 4 R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF RGB 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0 B1 B2 B3 ... Bxxx Bxxx
VPB[7:0]
G0
G1
G2
G3
...
Gxxx
Gxxx
VPC[7:0]
R0
R1
R2
R3
...
Rxxx
Rxxx
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 3.
Pixel encoding in RGB 4 : 4 : 4 (rising edge) input
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
10 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 7. YCBCR 4 : 4 : 4 mappings YCBCR 4 : 4 : 4 (3 x 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCBCR 4 : 4 : 4 CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCBCR 4 : 4 : 4 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCBCR 4 : 4 : 4 CR[0] CR[1] CR[2] CR[3] CR[4] CR[5] CR[6] CR[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCBCR 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] CB0 CB1 CB2 CB3 ... CBxxx CBxxx
VPB[7:0]
Y0
Y1
Y2
Y3
...
Yxxx
Yxxx
VPC[7:0]
CR0
CR1
CR2
CR3
...
CRxxx
CRxxx
001aag381
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4.
Pixel encoding in YCBCR 4 : 4 : 4 (rising edge) input
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
11 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 8. YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge mappings YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] CB[4] VPB[1] CB[5] VPB[2] CB[6] VPB[3] CB[7] VPB[4] CB[8] VPB[5] CB[9] VPB[6] CB[10] VPB[7] CB[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCBCR 4 : 2 : 2 used used used
Y0[10] CR[10] Y0[11] CR[11]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF CB0 Y0 CR0 Y1 ... CRxxx Yxxx
VPB[7:0]; VPA[3:0]
001aag383
Fig 5.
Pixel encoding YCBCR 4 : 2 : 2 ITU656-like external synchronization single edge (rising edge) input
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
12 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 9. YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge mappings YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] CB[4] VPB[1] CB[5] VPB[2] CB[6] VPB[3] CB[7] VPB[4] CB[8] VPB[5] CB[9] VPB[6] CB[10] VPB[7] CB[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCBCR 4 : 2 : 2 used used used
Y0[10] CR[10] Y0[11] CR[11]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF C B0 Y0 CR0 Y1 ... CRxxx Yxxx
VPB[7:0]; VPA[3:0]
001aag382
Fig 6.
Pixel encoding YCBCR 4 : 2 : 2 ITU656-like external synchronization double edge (rising and falling) input
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 10. YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge mappings YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] CB[4] VPB[1] CB[5] VPB[2] CB[6] VPB[3] CB[7] VPB[4] CB[8] VPB[5] CB[9] VPB[6] CB[10] VPB[7] CB[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCBCR 4 : 2 : 2 not used not used not used
Y0[10] CR[10] Y0[11] CR[11]
VCLK
VPB[7:0]; VPA[3:0]
CB0
Y0
CR0
Y1
...
CRxxx
Yxxx
001aag385
Fig 7.
Pixel encoding YCBCR 4 : 2 : 2 ITU656-like embedded synchronization single edge (rising edge) input
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 11. YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge mappings YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin YCBCR 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] VPB[0] CB[4] VPB[1] CB[5] VPB[2] CB[6] VPB[3] CB[7] VPB[4] CB[8] VPB[5] CB[9] VPB[6] CB[10] VPB[7] CB[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCBCR 4 : 2 : 2 not used not used not used
Y0[10] CR[10] Y0[11] CR[11]
VCLK
VPB[7:0]; VPA[3:0]
CB0
Y0
CR0
Y1
...
CRxxx
Yxxx
001aag384
Fig 8.
Pixel encoding YCBCR 4 : 2 : 2 ITU656-like embedded synchronization double edge (rising and falling) input
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 12. YCBCR 4 : 2 : 2 semi-planar external synchronization mappings YCBCR 4 : 2 : 2 semi-planar external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCBCR 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCBCR 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCBCR 4 : 2 : 2 semi-planar CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Control Pin YCBCR 4:2:2
HSYNC/HREF used VSYNC/VREF used DE/FREF used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Y0 Y1 Y2 Y3 Y4 Y5 ...
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
C B0
C R0
CB2
CR2
CB4
CR4
...
001aag386
Fig 9.
Pixel encoding YCBCR 4 : 2 : 2 semi-planar external synchronization (rising edge) input
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 13. YCBCR 4 : 2 : 2 semi-planar embedded synchronization mappings YCBCR 4 : 2 : 2 semi-planar embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCBCR 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCBCR 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCBCR 4 : 2 : 2 semi-planar CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Control Pin YCBCR 4:2:2
HSYNC/HREF not used VSYNC/VREF not used DE/FREF not used
VCLK
VPB[7:0]; VPA[3:0]
Y0
Y1
Y2
Y3
Y4
Y5
...
VPC[7:0]; VPA[7:4]
CB0
C R0
CB2
CR2
CB4
CR4
...
001aag387
Fig 10. Pixel encoding YCBCR 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input
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TDA9983B
150 MHz pixel rate HDMI transmitter
8.3 Synchronization
The TDA9983B can be synchronized with Hsync/Vsync external inputs or with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream.
8.3.1 Timing extraction generator
This block can extract the synchronization signals Href, Vref and Fref from Start Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data stream. Synchronization signals can be embedded in RGB, YCBCR 4 : 4 : 4, YCBCR 4 : 2 : 2 semi-planar (up to 2 x 12-bit), YCBCR 4 : 2 : 2 ITU656 and ITU656-like (up to 1 x 12-bit).
8.3.2 Data enable generator
The TDA9983B contains a Data Enable (DE) generator; this can generate an internal DE signal for a system which does not provide one.
8.4 Input and output video format
Due to the flexible video input formatter, the TDA9983B can accept a large range of input formats. This flexibility allows the TDA9983B to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler, downsampler and scaler) to be transmitted across the HDMI link. Table 14 gives the possible inputs and outputs.
Table 14. Input Color space RGB Format 4:4:4 Channels 3 x 8-bit no scaling no scaling no scaling YCBCR 4:4:4 3 x 8-bit no scaling no scaling no scaling YCBCR 4:2:2 up to 1 x 12-bit scalable scalable scalable up to 2 x 12-bit scalable scalable scalable Use of color space converter, upsampler, downsampler and scaler Scaler Output Color space RGB YCBCR YCBCR RGB YCBCR YCBCR YCBCR YCBCR RGB YCBCR YCBCR RGB Format 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 Channels 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit
8.5 Upsampler
The incoming YCBCR 4 : 2 : 2 (2 x 12-bit) data stream format could be upsampled into a 12-bit YCBCR 4 : 4 : 4 (3 x 12-bit) data stream by repeating or linearly interpolating the chrominance pixels.
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TDA9983B
150 MHz pixel rate HDMI transmitter
8.6 Color space converter
The color space converter is used to convert input video data from one type to another color space (RGB to YCBCR and YCBCR to RGB). This block can be bypassed and each coefficient is programmable via the I2C-bus register. Oin G\Y C 11 C 12 C 13 G\Y Y \G R\C + Oin C B \R = C 21 C 22 C 23 x R\C B B C R \B C 31 C 32 C 33 B\C R Oin B\C
R
Oout Y \G + Oout C B \R Oout C \B R
8.7 Downsampler
This block works only with YCBCR input format; these filters downsample the CB and CR signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the CB-CR channels.
8.8 Audio input format
The TDA9983B is compatible with HDMI 1.2a (DVD support). The TDA9983B can carry audio in I2S-bus format (one stereo up to four stereo channels) or in S/PDIF format. S/PDIF or I2S-bus format can be selected via the I2C-bus. Only one audio format can be used at a time: either S/PDIF or I2S-bus. Table 15 shows the audio port allocation.
Table 15. Audio port configuration All audio ports are LV-TTL compatible. Audio port AP0 AP1 AP2 AP3 AP4 AP5 AP6 AP7 ACLK I2S-bus and S/PDIF input configuration WS (word select) I2S-bus audio port 0 I2S-bus audio port 1 I2S-bus audio port 2 I2S-bus audio port 3 MCLK (master clock for S/PDIF) S/PDIF input AUX (internal test) SCK (I2S-bus clock)
8.9 S/PDIF
The audio port AP6 is used for the S/PDIF feature. In this format the TDA9983B supports 2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream up to 8 multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9983B is able to recover the original clock from the S/PDIF signal (no need for an external clock). In addition it can also use an external clock (MCLK) to decode the S/PDIF signal.
8.10 I2S-bus
The TDA9983B supports the NXP I2S-bus format. There are four I2S-bus stereo input channels (AP1 to AP4), which enable 8 uncompressed audio channels to be carried. The I2S-bus input interface receives an I2S-bus signal including serial data, word select and
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TDA9983B
150 MHz pixel rate HDMI transmitter
serial clock. Various I2S-bus formats are supported and can be selected by setting the appropriate bits of the register. The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency fs. Since the I2S-bus format is MSB aligned, audio data with an arbitrary precision can be received automatically. Audio samples with a precision better than 24 bits are truncated to 24 bits. If the input clock has a frequency of 32 x fs, only 16-bit audio samples can be received. In this case, the 8 LSBs will be set to logic 0. The serial data signal carries the serial baseband audio data, sample by sample left/right interleaved. The word select signal WS indicates whether left or right channel information is transferred over the serial data line. The formats for 16-bit and 32-bit modes are shown in Figure 11.
AP0/WS
left channel
right channel
ACLK 0R B23L B0L 0L 0L 0L B23R B0R 0R 0R 0R B23L
001aag915
APx x = 1, 2, 3, 4
a. 32-bit mode
AP0/WS
left channel
right channel
ACLK B0R B15L B14L B13L B2L B1L B0L B15R B14R B13R B2R B1R B0R B15L
001aag916
APx x = 1, 2, 3, 4
b. 16-bit mode Fig 11. NXP I2S-bus formats
8.11 Power management
The TDA9983B can be powered down via the I2C-bus register.
8.12 Interrupt controller
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has occurred (hot plug detect). This interrupt is maskable. Hot plug or unplug detect: pin HPD is the hot plug detection pin; it is 5 V input tolerant.
8.13 Initialization
Hard reset: after power-up, the TDA9983B is activated by a hard reset via pin RST_N. However, the TDA9983B has a power-on reset.
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TDA9983B
150 MHz pixel rate HDMI transmitter
8.14 HDMI
8.14.1 Output HDMI buffers
An external resistor must be used to set the HDMI output amplitude. It has to be connected between pin EXT_SWING and VDDH(3V3).
8.14.2 Pixel repetition
To transmit video formats with pixel rates below 25 Msample/s or to increase the number of audio sample packets in each frame, the TDA9983B uses pixel repetition to increase the transmitted pixel clock.
Table 16. 0 0 0 0 0 0 0 0 1 1 1 1 Pixel repetition SRL_PR[2] 0 0 0 0 1 1 1 1 0 0 0 1 SRL_PR[1] 0 0 1 1 0 0 1 1 0 0 1 x SRL_PR[0] 0 1 0 1 0 1 0 1 0 1 x x Pixel repeated no repetition once twice 3 times 4 times 5 times 6 times 7 times 8 times 9 times undefined undefined
SRL_PR[3]
8.14.3 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, in the `Vendor-Specific Data block' within the first CEA EDID timing extension. If the 24-bit IEEE registration identifier contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device will be treated as a DVI device. However, the TDA9983B does not have direct access to that information since E-EDID is read by an external microprocessor through the TDA9983B I2C-bus gate.
8.14.4 DDC channel
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard mode (100 kHz). 8.14.4.1 E-EDID reading In order to get receiver capabilities, the TDA9983B must read the E-EDID of the receiver. This is made possible by temporarily connecting the I2C-bus to the DDC lines, so that the microprocessor is able to read full EDID.
8.15 Scaler unit
The scaler unit has the following features:
* Upscaling only: to expand input image horizontally and vertically
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TDA9983B
150 MHz pixel rate HDMI transmitter
* Embedded deinterlacer (no need for output memory) * Maximum output operating frequency: 74.5 MHz (HDTV supported 1080i, 720p) * Input video standards (YCBCR 4 : 2 : 2 semi-planar, ITU656 and ITU656-like YCBCR,
no RGB and no YCBCR 4 : 4 : 4)
8.16 Input and output video scaler
The scaler converts the standard definition video signals (480i/576i, 480p/576p) into 720p, 1080i as illustrated in Figure 12.
VIDEO STANDARD OUTPUT 21, 22 (PAL) 576i x 720 6, 7 (NTSC)
FORMAT 861B
17, 18
2, 3
16
19
20
x 1280
1080i x 1920
1080p x 1920
x 1280
1080i x 1920
(1)
FORMAT 861B 2, 3 VIDEO STANDARD INPUT 4 5 6, 7 (NTSC) 16 17, 18 19 20 21, 22 (PAL) 31 720 1280 1920 720 1920 720 1280 1920 720 1920 x 480p x 720p x 1080i x 480i x 1080p x 576p x 720p x 1080i x 576i x 1080p
(1) (2) (3) (1) (1) (4) (5) (6) (1) (1) (1) (2) (3) (1)
(4) (5) (6) (1) (1)
001aag258
All upscaling modes are available only for YCBCR 4 : 2 : 2 input format. (1) Pass through (2) Upscaling (3) Upscaling and interlacing (4) Deinterlacing (5) Deinterlacing and upscaling (6) Deinterlacing, upscaling and interlacing
Fig 12. Input and output video scaler
8.17 I2C-bus interface
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode (400 kHz).
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
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1080p x 1920
720
720
x
x
480p
720p
576p
x
720
720p
480i
31
4
5
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9. I2C-bus register definitions
9.1 I2C-bus protocol
The registers of the TDA9983B can be accessed via the I2C-bus. The TDA9983B is used as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are supported. Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1. The I2C-bus device address is given in Table 17.
Table 17. A6 1 Device address R/W A4 1 A3 0 A2 0 A1 A1 A0 A0 1/0 A5 1
Device address
The I2C-bus access format is shown in Figure 13. For read access, the master writes the address of the TDA9983B, the subaddress to access the specific register and then the data.
123456789123456789123456789 SCL SDA SLAVE ADDRESS SUBADDRESS DATA STOP
001aaf292
Fig 13. I2C-bus access
9.2 Memory page management
The I2C-bus memory is split into several pages and the selection between pages is made with common register CURPAGE_ADR. It is only necessary to write in this register once to change the current page. So multiple read or write operations in the same page need a write register CURPAGE_ADR once at the beginning.
Table 18. 00h 01h 02h 10h 11h 12h Memory pages Memory page description General control Scaler PLL settings Information frames and packets Audio settings and content info packets HDMI and DVI Reference see Section 9.3 on page 23 see Section 9.4 on page 43 see Section 9.5 on page 55 see Section 9.6 on page 63 see Section 9.7 on page 81 see Section 9.8 on page 98
Page address
9.3 General control page register definitions
The current page address for the general control page is 00h. The configuration of the registers for this page is given in Table 19.
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Product data sheet Rev. 01 -- 20 May 2008
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NXP Semiconductors
Table 19. Register VERSION
I2C-bus registers of memory page 00h[1] Sub R/W addr 00h 01h 02h : 0Eh 0Fh 10h 11h : 1Fh 20h 21h 22h 23h 24h 25h 26h : 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch R W : R/W R/W : W W W W W W : W W W W W W W W W W W W W x x x x P13[7:0] x x x x P12[7:0] x P13[10:8] x x x x x x x x x x x x x x x x x x x x P11[7:0] x P12[10:8] MIRR_A MIRR_C MIRR_E EDGE TST_PAT x x TST_656 x SWAP_A[2:0] SWAP_C[2:0] SWAP_E[2:0] SP_SYNC[1:0] x x CCIR656 x : x x x x x MAT_BP MAT_SC[1:0] OFFSET_IN1[10:8] OFFSET_IN2[10:8] OFFSET_IN3[10:8] P11[10:8] x HPD_IN x x x SC_DEIL x SC_VID : MIRR_B MIRR_D MIRR_F EMB x V_TGL BLANKIT[1:0] SP_CNT[1:0] SWAP_B[2:0] SWAP_D[2:0] SWAP_F[2:0] H_TGL X_TGL CKCASE BLC[1:0] Bit 7 (MSB) 0 SCALER 6 1 x 5 1 x 4 0 CEHS : x SC_OUT x SC_IN HPD x x VS_RPT 3 0 CECS 2 0 DEHS 1 1 DECS 0 (LSB) 0 SR Default value 0110 0010 0000 0000 0000 0000 : 0000 0000 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0001 0010 0100 0101 0110 0001 0110 0000 0001 0000 0000 0000 0000 : 0000 0000 0000 0101 0000 0000 0000 0000 0000 0110 0000 0000 0000 0110 0000 0000 0000 0010 0000 0000 0000 0110 1001 0010 0000 0111 0101 0000
MAIN_CNTRL0 Not used : Not used INT_FLAGS_0 INT_FLAGS_1 Not used : Not used VIP_CNTRL_0 VIP_CNTRL_1 VIP_CNTRL_2 VIP_CNTRL_3 VIP_CNTRL_4 VIP_CNTRL_5 Not used : Not used MAT_CONTRL MAT_OI1_MSB MAT_OI1_LSB MAT_OI2_MSB MAT_OI2_LSB MAT_OI3_MSB MAT_OI3_LSB MAT_P11_MSB MAT_P11_LSB MAT_P12_MSB MAT_P12_LSB MAT_P13_MSB MAT_P13_LSB
150 MHz pixel rate HDMI transmitter
OFFSET_IN1[7:0] OFFSET_IN2[7:0] OFFSET_IN3[7:0]
TDA9983B
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Table 19. Register MAT_P21_MSB MAT_P21_LSB MAT_P22_MSB MAT_P22_LSB MAT_P23_MSB MAT_P23_LSB MAT_P31_MSB MAT_P31_LSB MAT_P32_MSB MAT_P32_LSB MAT_P33_MSB MAT_P33_LSB
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 00h[1] ...continued Sub R/W addr 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W x x x x x x x x x x x NLINE[7:0] x VS_LINE_START_1[10:8] VS_PIX_START_1[12:8] VS_PIX_START_1[7:0] VS_LINE_START_1[7:0] x x x NPIX[7:0] x NLINE[10:8] x x x x x x x x x PRESET_PIX[7:0] x x PRESET_LINE[10:8] NPIX[12:8] PRESET_LINE[7:0] x x x x x x x x x x x x x x x x P33[7:0] x x x VIDFORMAT[4:0] PRESET_PIX[12:8] OFFSET_OUT1[10:8] OFFSET_OUT2[10:8] OFFSET_OUT3[10:8] OFFSET_OUT1[7:0] OFFSET_OUT2[7:0] OFFSET_OUT3[7:0] x x x x P32[7:0] x P33[10:8] x x x x P31[7:0] x P32[10:8] x x x x P23[7:0] x P31[10:8] x x x x P22[7:0] x P23[10:8] Bit 7 (MSB) x 6 x 5 x 4 x P21[7:0] x P22[10:8] 3 x 2 1 P21[10:8] 0 (LSB) Default value 0000 0010 0000 0000 0000 0010 1100 1110 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0011 1000 1100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
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MAT_OO1_MSB MAT_OO1_LSB MAT_OO2_MSB MAT_OO2_LSB MAT_OO3_MSB MAT_OO3_LSB Not used VIDFORMAT REFPIX_MSB REFPIX_LSB REFLINE_MSB REFLINE_LSB NPIX_MSB NPIX_LSB NLINE_MSB NLINE_LSB VS_LINE_STRT_1_MSB VS_LINE_STRT_1_LSB VS_PIX_STRT_1_MSB VS_PIX_STRT_1_LSB
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 19. Register VS_LINE_END_1_MSB VS_LINE_END_1_LSB VS_PIX_END_1_MSB VS_PIX_END_1_LSB VS_LINE_STRT_2_MSB VS_LINE_STRT_2_LSB VS_PIX_STRT_2_MSB VS_PIX_STRT_2_LSB VS_LINE_END_2_MSB VS_LINE_END_2_LSB VS_PIX_END_2_MSB VS_PIX_END_2_LSB
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 00h[1] ...continued Sub R/W addr ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h C3h C4h C5h C6h C7h C8h C9h CAh CBh W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W SYNC_ ONCE x SYNC_ MTHD DWIN_DIS FRAME_ DIS x VHX_EXT[2:0] x x x DE_END[7:0] CBW[7:0] x x x VH_TGL[2:0] x x x x DE_START[7:0] DE_END[12:8] x x x x x x x x x x x x x x x HS_PIX_END[7:0] x x x x x x x x VWIN_START_1[10:8] VWIN_END_1[10:8] VWIN_START_2[10:8] VWIN_END_2[10:8] DE_START[12:8] VWIN_START_1[7:0] VWIN_END_1[7:0] VWIN_START_2[7:0] VWIN_END_2[7:0] x x x x x x x x x x x x x x x x x x x x x x Bit 7 (MSB) x 6 x 5 x 4 x 3 x 2 1 0 (LSB) VS_LINE_END_1[10:8] VS_PIX_END_1[12:8] VS_PIX_END_1[7:0] VS_LINE_START_2[10:8] VS_PIX_START_2[12:8] VS_PIX_START_2[7:0] VS_LINE_END_2[10:8] VS_PIX_END_2[12:8] VS_PIX_END_2[7:0] HS_PIX_START[12:8] HS_PIX_START[7:0] HS_PIX_END[12:8] VS_LINE_END_2[7:0] VS_LINE_START_2[7:0] Default value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Product data sheet 26 of 119
TDA9983B_1
NXP Semiconductors
VS_LINE_END_1[7:0]
HS_PIX_START_MSB HS_PIX_START_LSB HS_PIX_STOP_MSB HS_PIX_STOP_LSB VWIN_START_1_MSB VWIN_START_1_LSB VWIN_END_1_MSB VWIN_END_1_LSB VWIN_START_2_MSB VWIN_START_2_LSB VWIN_END_2_MSB VWIN_END_2_LSB DE_START_MSB DE_START_LSB DE_STOP_MSB DE_STOP_LSB COLBAR_WIDTH TBG_CNTRL_0 TBG_CNTRL_1
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 19. Register VBL_OFFSET_START VBL_OFFSET_END HBL_OFFSET_START HBL_OFFSET_END DWIN_RE_DE DWIN_FE_DE Not used : Not used HVF_CNTRL_0 HVF_CNTRL_1
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 00h[1] ...continued Sub R/W addr CCh CDh CEh CFh D0h D1h D2h : E3h E4h E5h E6h E7h E8h E9h EAh EBh : EDh EEh EFh F0h F1h F2h F3h : F7h F8h F9h FAh FBh W W W W W W : W W W W W : W W W W W : W W x x x x GHOST_XADDR[6:0] x x x x x x x x x x x x x NDIF_PF[7:0] x x x : x x x x A0_ZERO REPEAT[3:0] LEAD_OFFSET[3:0] TRAIL_OFFSET[3:0] IM_ CLKSEL WD_ CLKSEL x x TIM_M[7:0] TIM_L[7:0] : NDIV_IM[3:0] SM x RWB SEMI_ PLANAR x PAD[1:0] x x TIM_H[1:0] x Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) VBLOFF_START[7:0] VBLOFF_END[7:0] HBLOFF_START[7:0] HBLOFF_END[7:0] DWIN_RE_DE[7:0] DWIN_FE_DE[7:0] : PREFIL[1:0] VQR[1:0] INTPOL[1:0] YUVBLK FOR Default value 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0111 1010 0000 0000 : 0000 0000 0000 0000 0x00 0000 0000 0000 0000 0000 xx00 0001 1100 0010 0100 0000 0000 0000 : 0000 0000
Product data sheet 27 of 119
TDA9983B_1
NXP Semiconductors
Not used Not used TIMER_H TIMER_M TIMER_L Not used : Not used NDIV_IM NDIV_PF RPT_CNTRL LEAD_OFF TRAIL_OFF Not used : Not used For test GHOST_XADDR Not used Not used
150 MHz pixel rate HDMI transmitter
0000 0011 0001 1011 0000 0000 0000 0010 0000 0010 0000 0000 : 0000 0000 0000 0000 0110 0000 0000 0000 0000 0000
TDA9983B
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Table 19. Register Not used AIP_CLKSEL GHOST_ADDR CURPAGE_ADR
[1]
I2C-bus registers of memory page 00h[1] ...continued Sub R/W addr FCh FDh FEh FFh W W W Bit 7 (MSB) x 6 x 5 x 4 3 2 SEL_POL_ CLK 1 0 (LSB) Default value 0000 0000 0000 0000 1010 0001 0000 0000
Product data sheet Rev. 01 -- 20 May 2008 28 of 119
TDA9983B_1 (c) NXP B.V. 2008. All rights reserved.
NXP Semiconductors
SEL_AIP[1:0] GHOST_ADDR[6:0] CURPAGE_ADR[7:0]
SEL_FS[1:0] GHOST_ DIS
R: reading register W: writing register x: bit must be set to default value for proper operation -: not used
150 MHz pixel rate HDMI transmitter
TDA9983B
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.3.1 Main control register
Table 20. VERSION register (address 00h) bit description Legend: * = default value Bit 7 to 4 3 to 0 Symbol Access Value R R 0110 0010 Description TDA9983B device version die version
Table 21. MAIN_CNTRL0 register (address 01h) bit description Legend: * = default value Bit 7 Symbol SCALER Access Value W 0* 1 6 to 5 4 x CEHS W W 0* 1 3 CECS W 0* 1 2 DEHS W 0* 1 1 DECS W 0* 1 0 SR W 0* 1 00* Description scaler HDMI video formatter uses vip-output (scaler is bypassed) HDMI video formatter uses scaler-output undefined I2C-bus enable high speed I2C_SDA and I2C_SCL set to Standard or Fast mode I2C_SDA and I2C_SCL set to High-speed mode I2C-bus enable current source
I2C_SCL pull-up current source disabled I2C_SCL pull-up current source enabled DDC-bus enable high speed DDC_SDA and DDC_SCL set to Standard or Fast mode DDC_SDA and DDC_SCL set to High-speed mode DDC-bus enable current source DDC_SCL pull-up current source disabled DDC_SCL pull-up current source enabled soft reset no specific action soft reset for all modules which do not use the cclk clock domain
9.3.2 Interrupt flags/masks registers
Table 22. INT_FLAGS_0 register (address 0Fh) bit description Legend: * = default value Bit 7 to 2 1 Symbol x HPD Access Value R/W R/W 0* 1 0 x R/W 0* Description HPD: transition on HPD input FALSE/INT_disabled TRUE/INT_enabled undefined 0000 00* undefined
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
29 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 23. INT_FLAGS_1 register (address 10h) bit description Legend: * = default value Bit 7 Symbol HPD_IN Access Value R/W 0* 1 6 5 x SC_DEIL R/W R/W 0* 1 4 SC_VID R/W 0* 1 3 SC_OUT R/W 0* 1 2 SC_IN R/W 0* 1 1 0 x VS_RPT R/W R/W 0* 1 0* 0* Description HPD input: transition on HPD input HPD is LOW HPD is HIGH undefined scaler deinterlace: scaler deinterlaced video buffer failure FALSE/INT_disabled TRUE/INT_enabled scaler video: scaler primary video buffer full failure FALSE/INT_disabled TRUE/INT_enabled scaler output: scaler output failure FALSE/INT_disabled TRUE/INT_enabled scaler input: scaler input failure FALSE/INT_disabled TRUE/INT_enabled undefined rising edge on VS_RPT detected FALSE/INT_disabled TRUE/INT_enabled
9.3.3 Video input processing control registers
Table 24. VIP_CNTRL_0 register (address 20h) bit description Legend: * = default value Bit 7 Symbol MIRR_A Access Value W 0* 1 6 to 4 SWAP_A[2:0] W 000* 001 010 011 100 other 3 MIRR_B W 0* 1 Description mirror A no specific action mirror nibble; m[23:20] = s[20:23] swap A selector pin VPC[7:4] = vp[23:20] pin VPC[3:0] = vp[23:20] pin VPB[7:4] = vp[23:20] pin VPB[3:0] = vp[23:20] pin VPA[7:4] = vp[23:20] pin VPA[3:0] = vp[23:20] mirror B no specific action mirror nibble; m[19:16] = s[16:19]
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 24. VIP_CNTRL_0 register (address 20h) bit description ...continued Legend: * = default value Bit 2 to 0 Symbol SWAP_B[2:0] Access Value W 000 001* 010 011 100 other Description swap B selector pin VPC[7:4] = vp[19:16] pin VPC[3:0] = vp[19:16] pin VPB[7:4] = vp[19:16] pin VPB[3:0] = vp[19:16] pin VPA[7:4] = vp[19:16] pin VPA[3:0] = vp[19:16]
Table 25. VIP_CNTRL_1 register (address 21h) bit description Legend: * = default value Bit 7 Symbol MIRR_C Access Value W 0* 1 6 to 4 SWAP_C[2:0] W 000 001 010* 011 100 other 3 MIRR_D W 0* 1 2 to 0 SWAP_D[2:0] W 000 001 010 011 100* other Description mirror C no specific action mirror nibble; m[15:12] = s[12:15] swap C selector pin VPC[7:4] = vp[15:12] pin VPC[3:0] = vp[15:12] pin VPB[7:4] = vp[15:12] pin VPB[3:0] = vp[15:12] pin VPA[7:4] = vp[15:12] pin VPA[3:0] = vp[15:12] mirror D no specific action mirror nibble; m[11:8] = s[8:11] swap D selector pin VPC[7:4] = vp[11:8] pin VPC[3:0] = vp[11:8] pin VPB[7:4] = vp[11:8] pin VPB[3:0] = vp[11:8] pin VPA[7:4] = vp[11:8] pin VPA[3:0] = vp[11:8]
Table 26. VIP_CNTRL_2 register (address 22h) bit description Legend: * = default value Bit 7 Symbol MIRR_E Access Value W 0* 1 Description mirror E no specific action mirror nibble; m[7:4] = s[4:7]
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
31 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 26. VIP_CNTRL_2 register (address 22h) bit description ...continued Legend: * = default value Bit 6 to 4 Symbol SWAP_E[2:0] Access Value W 000 001 010 011 100 101* other 3 MIRR_F W 0* 1 2 to 0 SWAP_F[2:0] W 000 001 010 011 100 110* other Description swap E selector pin VPC[7:4] = vp[7:4] pin VPC[3:0] = vp[7:4] pin VPB[7:4] = vp[7:4] pin VPB[3:0] = vp[7:4] pin VPA[7:4] = vp[7:4] pin VPA[3:0] = vp[7:4] pin VPA[3:0] = vp[7:4] mirror F no specific action mirror nibble; m[3:0] = s[0:3] swap F selector pin VPC[7:4] = vp[3:0] pin VPC[3:0] = vp[3:0] pin VPB[7:4] = vp[3:0] pin VPB[3:0] = vp[3:0] pin VPA[7:4] = vp[3:0] pin VPA[3:0] = vp[3:0] pin VPA[3:0] = vp[3:0]
Table 27. VIP_CNTRL_3 register (address 23h) bit description Legend: * = default value Bit 7 Symbol EDGE Access Value W 0* 1 6 5 to 4 x SP_SYNC[1:0] W W 00 01* 10 11 3 EMB W 0* 1 2 V_TGL W 0 1* 0* Description edge vp-bus synchronized on positive edge of vip_clk_m vp-bus synchronized on negative edge of vip_clk_m undefined sp synchronization sp_cnt synchronized by hemb sp_cnt synchronized by rising edge de sp_cnt synchronized by rising edge of hs sp_cnt fixed at i2c_sp_cnt embedded no specific action use embedded synchronization codes v_toggle no specific action toggle vs/vref
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
32 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 27. VIP_CNTRL_3 register (address 23h) bit description ...continued Legend: * = default value Bit 1 Symbol H_TGL Access Value W 0 1* 0 X_TGL W 0* 1 Description h_toggle no specific action toggle hs/href x_toggle no specific action toggle de/fref
Table 28. VIP_CNTRL_4 register (address 24h) bit description Legend: * = default value Bit 7 Symbol TST_PAT Access Value W 0* 1 6 TST_656 W 0* 1 5 4 x CCIR656 W W 0* 1 3 to 2 BLANKIT[1:0] W 00* 01 10 11 1 to 0 BLC[1:0] W 00 01* 10 11 0* Description test pattern no specific action insert test pattern with high data activity test 656: test mode (ITU656 via audio port AP) no specific action inject ITU656 video via audio port undefined CCIR 656: ITU656 or ITU656-like at the input no specific action activate ITU data demultiplexing (from ITU656 or ITU656-like to 4 : 2 : 2 semi-planar) blankit: select source for blankit control not de hs AND vs (not hs) AND vs hemb AND vemb blanking codes no insertion of blanking codes or test pattern blanking codes set to RGB 4 : 4 : 4 levels blanking codes set to YUV 4 : 4 : 4 levels blanking codes set to YUV 4 : 2 : 2 levels
Table 29. VIP_CNTRL_5 register (address 25h) bit description Legend: * = default value Bit 7 to 3 2 to 1 Symbol x SP_CNT[1:0] Access Value W W 00* 01 10 11
TDA9983B_1
Description sp counter sp_cnt preset to '00' sp_cnt preset to '01' sp_cnt preset to '10' sp_cnt preset to '11'
(c) NXP B.V. 2008. All rights reserved.
0000 0* undefined
Product data sheet
Rev. 01 -- 20 May 2008
33 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 29. VIP_CNTRL_5 register (address 25h) bit description ...continued Legend: * = default value Bit 0 Symbol CKCASE Access Value W 0* 1 Description ckcase no specific action toggle clk1case (phase clk1 with respect to clk2)
9.3.4 Color space conversion registers
Table 30. MAT_CONTRL register (address 80h) bit description Legend: * = default value Bit 7 to 3 2 Symbol x MAT_BP Access Value W W 0 1* 1 and 0 MAT_SC[1:0] W Description matrix bypassed: bypasses or not the matrix and offsets uses color space conversion bypasses matrix scale factor selection: sets the scale factor to convert the floating matrix [Cxy] into an integer matrix [Pxy]: 0000 0* undefined
P 11 P 12 P 13 P 31 P 32 P 33
C 11 C 12 C 13 C 31 C 32 C 33
P 21 P 22 P 23 = INT (S x C 21 C 22 C 23 )
The choice depends on the biggest coefficient in absolute value |Cxy| 00 01* 10 11 Table 31. Offset input registers (address 81h to 86h) bit description Legend: * = default value Address 81h 82h 83h 84h 85h 86h
[1]
when 2 |Cxy| < 4; S = 256 when 1 |Cxy| < 2; S = 512 when |Cxy| < 1; S = 1024 undefined
Register
Bit
Symbol
Access Value W W W W W W W W W 000* 00h* 110* 00h* 110* 00h*
Description offset input 1: compensates the brightness value for the G/Y channel[1]
MAT_OI1_MSB 7 to 3 x 2 to 0 OFFSET_IN1[10:8] MAT_OI1_LSB 7 to 0 OFFSET_IN1[7:0] 2 to 0 OFFSET_IN2[10:8] MAT_OI2_LSB 7 to 0 OFFSET_IN2[7:0] 2 to 0 OFFSET_IN3[10:8] MAT_OI3_LSB 7 to 0 OFFSET_IN3[7:0] MAT_OI3_MSB 7 to 3 x MAT_OI2_MSB 7 to 3 x
0000 0* undefined
0000 0* undefined offset input 2: compensates the brightness value for the R/CR channel[1]
0000 0* undefined offset input 3: compensates the brightness value for the B/CB channel[1]
The value is a signed 11-bit two's complement integer.
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
34 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 32. Coefficient registers (address 87h to 98h) bit description Legend: * = default value Address 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h
[1]
Register MAT_P11_MSB MAT_P11_LSB MAT_P12_MSB MAT_P12_LSB MAT_P13_MSB MAT_P13_LSB MAT_P21_MSB MAT_P21_LSB MAT_P22_MSB MAT_P22_LSB MAT_P23_MSB MAT_P23_LSB MAT_P31_MSB MAT_P31_LSB MAT_P32_MSB MAT_P32_LSB MAT_P33_MSB MAT_P33_LSB
Bit
Symbol
Access Value W W W W W W W W W W W W W W W W W W W W W W W W W W W 010* 00h* 110* 92h* 111* 50h* 010* 00h* 010* CEh* 000* 00h* 010* 00h* 000* 00h* 011* 8Ch*
Description coefficient (1, 1): coefficient from the G/Y channel to the G/Y channel[1]
7 to 3 x 2 to 0 P11[10:8] 7 to 0 P11[7:0] 7 to 3 x 2 to 0 P12[10:8] 7 to 0 P12[7:0] 7 to 3 x 2 to 0 P13[10:8] 7 to 0 P13[7:0] 7 to 3 x 2 to 0 P21[10:8] 7 to 0 P21[7:0] 7 to 3 x 2 to 0 P22[10:8] 7 to 0 P22[7:0] 7 to 3 x 2 to 0 P23[10:8] 7 to 0 P23[7:0] 7 to 3 x 2 to 0 P31[10:8] 7 to 0 P31[7:0] 7 to 3 x 2 to 0 P32[10:8] 7 to 0 P32[7:0] 7 to 3 x 2 to 0 P33[10:8] 7 to 0 P33[7:0]
0000 0* undefined
0000 0* undefined coefficient (1, 2): coefficient from the R/CR channel to the G/Y channel[1]
0000 0* undefined coefficient (1, 3): coefficient from the B/CB channel to the G/Y channel[1]
0000 0* undefined coefficient (2, 1): coefficient from the G/Y channel to the R/CR channel[1]
0000 0* undefined coefficient (2, 2): coefficient from the R/CR channel to the R/CR channel[1]
0000 0* undefined coefficient (2, 3): coefficient from the B/CB channel to the R/CR channel[1]
0000 0* undefined coefficient (3, 1): coefficient from the G/Y channel to the B/CB channel[1]
0000 0* undefined coefficient (3, 2): coefficient from the R/CR channel to the B/CB channel[1]
0000 0* undefined coefficient (3, 3): coefficient from the B/CB channel to the B/CB channel[1]
The value is a signed 11-bit two's complement integer.
Table 33. Offset output registers (address 99h to 9Eh) bit description Legend: * = default value Address Register 99h 9Ah 9Bh 9Ch MAT_OO1_MSB MAT_OO1_LSB MAT_OO2_MSB MAT_OO2_LSB Bit Symbol Access Value W W W W 000* 00h* 000* 00h* Description offset output 1: new clamp level for the G/Y channel[1] 7 to 3 x 7 to 0 OFFSET_OUT1[7:0] 7 to 3 x 7 to 0 OFFSET_OUT2[7:0] 0000 0* undefined
2 to 0 OFFSET_OUT1[10:8] W
0000 0* undefined offset output 2: new clamp level for the R/CR channel[1]
2 to 0 OFFSET_OUT2[10:8] W
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
35 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 33. Offset output registers (address 99h to 9Eh) bit description ...continued Legend: * = default value Address Register 9Dh 9Eh
[1]
Bit
Symbol
Access Value W W 000* 00h*
Description offset output 3: new clamp level for the B/CB channel[1]
MAT_OO3_MSB MAT_OO3_LSB
7 to 3 x 7 to 0 OFFSET_OUT3[7:0]
0000 0* undefined
2 to 0 OFFSET_OUT3[10:8] W
The value is a signed 11-bit two's complement integer.
9.3.5 Video format registers
Table 34. VIDFORMAT register (address A0h) bit description Legend: * = default value Bit Symbol Access Value W 000* 0 0000* 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 0 1001 0 1010 0 1011 others Description undefined video format: see EIA/CEA-861B specification 640 x 480p at 60 Hz (format 1 (VGA)) 720 x 480p at 60 Hz (format 2/3) 1280 x 720p at 60 Hz (format 4) 1920 x 1080i at 60 Hz (format 5) 720 x 480i at 60 Hz (format 6/7) 720 x 240p at 60 Hz (format 8/9) 1920 x 1080p at 60 Hz (format 16) 720 x 576p at 50 Hz (format 17/18) 1280 x 720p at 50 Hz (format 19) 1920 x 1080i at 50 Hz (format 20) 720 x 576i at 50 Hz (format 21/22) 720 x 288p at 50 Hz (format 23/24) 1920 x 1080p at 50 Hz (format 31) 7 to 5 x
4 to 0 VIDFORMAT[4:0] W
Table 35. REFPIX_xxx, REFLINE_xxx, NPIX_xxx and NLINE_xxx registers (address A1h to A8h) bit description Legend: * = default value Address Register A1h A2h A3h A4h A5h A6h A7h A8h REFPIX_MSB REFPIX_LSB REFLINE_MSB REFLINE_LSB NPIX_MSB NPIX_LSB NLINE_MSB NLINE_LSB Bit Symbol Access Value W W W W W W W W W W W W 000* Description undefined 7 to 5 x 4 to 0 PRESET_PIX[12:8] 7 to 0 PRESET_PIX[7:0] 7 to 3 x 2 to 0 PRESET_LINE[10:8] 7 to 0 PRESET_LINE[7:0] 7 to 5 x 4 to 0 NPIX[12:8] 7 to 0 NPIX[7:0] 7 to 3 x 2 to 0 NLINE[10:8] 7 to 0 NLINE[7:0]
0 0000* preset pixel: reference pixel preset 01h* 0000 0* undefined 000* 01h* 000* preset line: reference line preset undefined
0 0000* number pixel: number of pixels per line 00h* 0000 0* undefined 000* 00h* number line: number of lines per frame
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
36 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
VS_LINE_STRT_xx, VS_PIX_STRT_xx, VS_LINE_END_xx, VS_PIX_END_xx registers (address A9h to B8h) bit description Legend: * = default value Address Register A9h AAh Bit Symbol Access Value W W 000* 00h* Description vertical synchronization line start 1: vertical synchronization line number for start pulse in field 1 undefined VS_LINE_STRT_1_MSB 7 to 3 x VS_LINE_STRT_1_LSB 7 to 0 VS_LINE_START_1[7:0] 0000 0* undefined
Table 36.
2 to 0 VS_LINE_START_1[10:8] W
ABh ACh
VS_PIX_STRT_1_MSB VS_PIX_STRT_1_LSB
7 to 5 x 4 to 0 VS_PIX_START_1[12:8] 7 to 0 VS_PIX_START_1[7:0]
W W W
000*
0 0000* vertical synchronization pixel start 1: vertical synchronization 00h* pixel number for start pulse in field 1 0000 0* undefined 000* 00h* vertical synchronization line end 1: vertical synchronization line number for end pulse in field 1 undefined
ADh AEh
VS_LINE_END_1_MSB VS_LINE_END_1_LSB
7 to 3 x 2 to 0 VS_LINE_END_1[10:8] 7 to 0 VS_LINE_END_1[7:0]
W W W
AFh B0h
VS_PIX_END_1_MSB VS_PIX_END_1_LSB
7 to 5 x 4 to 0 VS_PIX_END_1[12:8] 7 to 0 VS_PIX_END_1[7:0]
W W W
000*
0 0000* vertical synchronization pixel end 1: vertical synchronization 00h* pixel number for end pulse in field 1 0000 0* undefined 000* 00h* vertical synchronization line start 2: vertical synchronization line number for start pulse in field 2 undefined
B1h B2h
VS_LINE_STRT_2_MSB 7 to 3 x VS_LINE_STRT_2_LSB 7 to 0 VS_LINE_START_2[7:0]
W W
2 to 0 VS_LINE_START_2[10:8] W
B3h B4h
VS_PIX_STRT_2_MSB VS_PIX_STRT_2_LSB
7 to 5 x 4 to 0 VS_PIX_START_2[12:8] 7 to 0 VS_PIX_START_2[7:0]
W W W
000*
0 0000* vertical synchronization pixel start 2: vertical synchronization 00h* pixel number for start pulse in field 2 0000 0* undefined 000* 00h* vertical synchronization line end 2: vertical synchronization line number for end pulse in field 2 undefined
B5h B6h
VS_LINE_END_2_MSB VS_LINE_END_2_LSB
7 to 3 x 2 to 0 VS_LINE_END_2[10:8] 7 to 0 VS_LINE_END_2[7:0]
W W W
B7h B8h
VS_PIX_END_2_MSB VS_PIX_END_2_LSB
7 to 5 x 4 to 0 VS_PIX_END_2[12:8] 7 to 0 VS_PIX_END_2[7:0]
W W W
000*
0 0000* vertical synchronization pixel end 2: vertical synchronization 00h* pixel number for end pulse in field 2
TDA9983B_1
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Product data sheet
Rev. 01 -- 20 May 2008
37 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 37. HS_PIX_xx registers (address B9h to BCh) bit description Legend: * = default value Address Register B9h BAh BBh BCh HS_PIX_START_MSB HS_PIX_START_LSB HS_PIX_STOP_MSB HS_PIX_STOP_LSB Bit Symbol Access Value W W W W W W 000* Description undefined 7 to 5 x 4 to 0 HS_PIX_START[12:8] 7 to 0 HS_PIX_START[7:0] 7 to 5 x 4 to 0 HS_PIX_END[12:8] 7 to 0 HS_PIX_END[7:0]
0 0000* horizontal synchronization pixel number for start pulse in field 1 00h* 000* undefined 0 0000* horizontal synchronization pixel number for end pulse in field 2 00h*
Table 38. VWIN_START_xx and VWIN_END_xx registers (address BDh and C4h) bit description Legend: * = default value Address Register BDh BEh BFh C0h C1h C2h C3h C4h VWIN_START_1_MSB VWIN_START_1_LSB VWIN_END_1_MSB VWIN_END_1_LSB VWIN_START_2_MSB VWIN_START_2_LSB VWIN_END_2_MSB VWIN_END_2_LSB Bit Symbol Access Value W W W W W W W W W W W W 000* 00h* Description vertical window start 1: vertical window line number for start pulse in field 1 vertical window end 1: vertical window line number for end pulse in field 1 vertical window start 2: vertical window line number for start pulse in field 2 vertical window end 2: vertical window line number for end pulse in field 2 7 to 3 x 2 to 0 VWIN_START_1[10:8] 7 to 0 VWIN_START_1[7:0] 7 to 3 x 2 to 0 VWIN_END_1[10:8] 7 to 0 VWIN_END_1[7:0] 7 to 3 x 2 to 0 VWIN_START_2[10:8] 7 to 0 VWIN_START_2[7:0] 7 to 3 x 2 to 0 VWIN_END_2[10:8] 7 to 0 VWIN_END_2[7:0] 0000 0* undefined
0000 0* undefined 000* 00h*
0000 0* undefined 000* 00h*
0000 0* undefined 000* 00h*
Table 39. DE_xxx registers (address C5h to C8h) bit description Legend: * = default value Address Register C5h C6h C7h C8h DE_START_MSB DE_START_LSB DE_STOP_MSB DE_STOP_LSB Bit Symbol Access Value W W W W W W 000* Description undefined 7 to 5 x 4 to 0 DE_START[12:8] 7 to 0 DE_START[7:0] 7 to 5 x 4 to 0 DE_END[12:8] 7 to 0 DE_END[7:0]
0 0000* data enable start: data enable pixel number for start pulse in 00h* field 1 000* undefined 0 0000* data enable end: data enable pixel number for end pulse in 00h* field 2
Table 40. COLBAR_WIDTH register (address C9h) bit description Legend: * = default value Bit 7 to 0 Symbol CBW[7:0] Access W Value 00h* Description color bar width
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
38 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 41. TBG_CNTRL_0 register (address CAh) bit description Legend: * = default value Bit 7 Symbol SYNC_ONCE Access Value W 0* 1 6 SYNC_MTHD W 0* 1 5 FRAME_DIS W 0* 1 4 to 0 x W 0 0000* Description sync once line/pixel counters are synchronized each frame line/pixel counters are synchronized only once sync method synchronization is based on combination of v and h synchronization is based on combination of v and x (de) frame disable: synchronized by linecnt = 1 AND pixelcnt = 1 enable video frames disable video frames undefined
Table 42. TBG_CNTRL_1 register (address CBh) bit description Legend: * = default value Bit 7 6 Symbol x DWIN_DIS Access Value W W 0* 1 5 VHX_EXT[2] W 0* 1 4 VHX_EXT[1] W 0* 1 3 VHX_EXT[0] W 0* 1 2 VH_TGL[2] W 0* 1 1 VH_TGL[1] W 0* 1 0 VH_TGL[0] W 0* 1
TDA9983B_1
Description undefined data island window disable data island window active data island window disabled vhx_ext 2: bit 2 vs = vs_tbg (internal) vs = v_vip (external) vhx_ext 1: bit 1 hs = hs_tbg (internal) hs = h_vip (external) vhx_ext 0: bit 0 de = de_tbg (internal) de = x_vip (external) vh_tgl 2: bit 2 vs/hs-polarity is determined by vidformat_table vs/hs-polarity depends on VH_TGL[1:0] vh_tgl 1: bit 1 no specific action toggle vs (only when VH_TGL[2] = 1) vh_tgl 0: bit 0 no specific action toggle hs (only when VH_TGL[2] = 1)
(c) NXP B.V. 2008. All rights reserved.
0*
Product data sheet
Rev. 01 -- 20 May 2008
39 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 43. OFFSET registers (address CCh to CFh) bit description Legend: * = default value Address Register CCh VBL_OFFSET_START Bit 7 to 0 Symbol VBLOFF_START[7:0] Access Value Description W 00h* vertical blanking offset start: vertical blanking offset at start active window vertical blanking offset end: vertical blanking offset at end active window horizontal blanking offset start: horizontal blanking offset at start active window horizontal blanking offset end: horizontal blanking offset at end active window
CDh
VBL_OFFSET_END
7 to 0
VBLOFF_END[7:0]
W
00h*
CEh
HBL_OFFSET_START
7 to 0
HBLOFF_START[7:0]
W
00h*
CFh
HBL_OFFSET_END
7 to 0
HBLOFF_END[7:0]
W
00h*
Table 44. DWIN_xx_DE registers (address D0h and D1h) bit description Legend: * = default value Address Register D0h DWIN_RE_DE Bit 7 to 0 Symbol DWIN_RE_DE[7:0] Access Value Description W 11h* data window rising edge data enable: data island window rising edge offset with respect to data enable data window falling edge data enable: data island window falling edge offset with respect to data enable
D1h
DWIN_FE_DE
7 to 0
DWIN_FE_DE[7:0]
W
7Ah*
9.3.6 HDMI video formatter control registers
Table 45. HVF_CNTRL_0 register (address E4h) bit description Legend: * = default value Bit 7 Symbol SM Access W 0* 1 6 RWB W 0* 1 5 to 4 3 to 2 x PREFIL[1:0] W W 00* 01 10 11 00* Value Description service mode no specific action service mode (color bar inserted in video path) red, white, blue 4-bar color bar (Red - White - Blue - Black) 8-bar color bar (White - Yellow - Magenta Red - Cyan - Green - Blue - Black) undefined prefilter no prefilter [1 2 1] [-1 0 9 16 9 0 -1] 27 taps ITU601-compliant halfband filter
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
40 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 45. HVF_CNTRL_0 register (address E4h) bit description ...continued Legend: * = default value Bit 1 to 0 Symbol INTPOL[1:0] Access W 00* 01 10 11 Value Description interpolation bypass (from 4 : 4 : 4 to 4 : 4 : 4) intpol_by_2 (from 4 : 2 : 2 to 4 : 4 : 4); copy sample intpol_by_2 (from 4 : 2 : 2 to 4 : 4 : 4); linear interpolation ([1 2 1] / 2 filter) undefined
Table 46. HVF_CNTRL_1 register (address E5h) bit description Legend: * = default value Bit 7 6 Symbol x SEMI_PLANAR Access W W 0 1 5 to 4 PAD[1:0] W 00* 01 10 11 3 to 2 VQR[1:0] W 00* 01 10 Value 0* Description undefined semi-planar 4 : 4 : 4 at the input of the vrf-module 4 : 2 : 2 at the input of the vrf-module pad 12-bit data path 8-bit data path; 4 LSBs set to 0000 10-bit data path; 2 LSBs set to 00 10-bit data path; 2 LSBs set to 00 video quantization range full-scale RGB/YUV (max. 235 to min. 16) Y (max. 235 to min. 16); U (max. 240 to min. 16); V (max. 240 to min. 16) Y (max. 235 to min. 16); U (max. 240 to min. 16); V (max. 240 to min. 16) YUV blank 0* 1 0 FOR W 0* 1 UV blank level = 16 UV blank level = 0 formatter transparent formatter (4 : 4 : 4 or 4 : 2 : 2 unprocessed) 4 : 2 : 2 output format (4 : 4 : 4 to 4 : 2 : 2 conversion active)
11
1
YUVBLK
W
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
41 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.3.7 Timer control registers
Table 47. Timer control registers (address E8h to EAh) bit description Legend: * = default value Address E8h Register TIMER_H Bit 7 Symbol IM_CLKSEL Access Value W 0 1 6 WD_CLKSEL W 0 1 5 to 2 1 to 0 x TIM_H[1:0] W W 00 01* 10 00 E9h EAh TIMER_M TIMER_L 7 to 0 7 to 0 TIM_M[7:0] TIM_L[7:0] W C2h* W 40h* 0000* Description im timer clock select ddc_master clocked by hdmi_clk / (NDIV_IM[3:0] + 1) ddc_master clocked by cclk / 3 (typically 10 MHz) watchdog timer clock select wd_timer clocked by hdmi_clk / (NDIV_PF[7:0] + 1) wd_timer clocked by cclk / 32 undefined timer control register height tim[17:16] = '00' tim[17:16] = '01' tim[17:16] = '10' tim[17:16] = '11' timer control register medium tim[15:8] = TIM_M[7:0] timer control register low tim[7:0] = TIM_L[7:0]
9.3.8 NDIV register
Table 48. NDIV_xxx registers (address EEh and EFh) bit description Legend: * = default value Address EEh Register NDIV_IM Bit 7 to 4 3 to 0 Symbol x NDIV_IM[3:0] Access Value W W 0011* EFh NDIV_PF 7 to 0 NDIV_PF[7:0] W 1Bh* 0000* Description undefined N divisor DDC-bus master N divisor to set clock period for DDC-bus master N divisor pixel frequency N divisor to set clock period for timers (equals pixel frequency)
9.3.9 Control registers
Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description Legend: * = default value Address F0h F1h Register RPT_CNTRL LEAD_OFF Bit 7 to 4 3 to 0 7 to 4 3 to 0 Symbol x REPEAT[3:0] x LEAD_OFFSET[3:0] Access Value W W W W 0000* 0000* 0000* 0010* Description undefined repeat: repeater control undefined leading offset: leading offset for dwin (in case rpt > 1)
(c) NXP B.V. 2008. All rights reserved.
TDA9983B_1
Product data sheet
Rev. 01 -- 20 May 2008
42 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 49. Control registers (address F0h to F2h, F9h, FDh and FEh) bit description ...continued Legend: * = default value Address F2h Register TRAIL_OFF Bit 7 to 4 3 to 0 F9h GHOST_XADDR 7 to 1 0 FDh AIP_CLKSEL 7 to 5 4 to 3 Symbol x TRAIL_OFFSET[3:0] Access Value W W 0000* 0010* 0110 000* 0* 000* 00* 01 1X 2 1 to 0 SEL_POL_CLK SEL_FS[1:0] W W 00* 01 1X FEh GHOST_ADDR 7 to 1 0 GHOST_ADDR[6:0] GHOST_DIS W W 1010 000* 1* 0* Description undefined trailing offset: trailing offset for dwin (in case rpt > 1) ghost extended address undefined selection audio input S/PDIF I2S-bus for internal use select polarity clock: for internal use select fs: CTS reference aclk mclk fs_64 (S/PDIF) ghost address -
GHOST_XADDR[6:0] W A0_ZERO x SEL_AIP[1:0] W W W
9.3.10 Current page address register
Table 50. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol CURPAGE_ADR[7:0] Access Value W 00h* Description current page address: selects the current memory page
9.4 Scaler page register definitions
The current page address for the Scaler page is 01h. The configuration of the registers for this page is given in Table 51.
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
43 of 119
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Product data sheet Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved. TDA9983B_1
NXP Semiconductors
Table 51. Register
I2C-bus registers of memory page 01h[1] Sub R/W addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh W W W W W W W W W W W W W W R R R R R R R R R R R R R W W W W x x x x x x x x x x x x x x x x x x x x x VS_LUT0[7:0] VS_LUT1[7:0] VS_LUT2[7:0] VS_LUT3[7:0] x x x x x x x x x x x x x x x x x x x x x Bit 7 (MSB) x x x x x x x x x NPIX_IN[7:0] x x x x x x x x x x x x x NPIX_IN[9:8] NPIX_OUT[10:8] NLINE_IN[9:8] NLINE_OUT[9:8] NLINE_SKIP[2:0] NPIX_OUT[7:0] NLINE_IN[7:0] NLINE_OUT[7:0] 6 x 5 x 4 VID_FORMAT_O[2:0] x IL_OUT_ ON 3 2 PHASES_ V 1 VS_ON 0 (LSB) DEIL_ON LUT_SEL[1:0] VID_FORMAT_I[2:0] Default value 0000 0000 0000 0000 0001 1110 0001 0000 0000 0000 1101 0000 0000 0010 1101 0000 0000 0010 0100 0000 0000 0010 0100 0000 0000 0010 0000 0000 XXXX XXXX XXXX XXXX MAX_BUFFILL_P[11:8] MAX_BUFFILL_D[11:8] MAX_FIFOFILL_PI[4:0] MIN_FIFOFILL_PO1[4:0] MIN_FIFOFILL_PO2[4:0] MIN_FIFOFILL_PO3[4:0] MIN_FIFOFILL_PO4[4:0] MAX_FIFOFILL_DI[4:0] MAX_FIFOFILL_DO[4:0] XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
SC_VIDFORMAT SC_CNTRL SC_DELTA_PHASE_V SC_DELTA_PHASE_H SC_START_PHASE_H SC_NPIX_IN_LSB SC_NPIX_IN_MSB SC_NPIX_OUT_LSB SC_NPIX_OUT_MSB SC_NLINE_IN_LSB SC_NLINE_IN_MSB SC_NLINE_OUT_LSB SC_NLINE_OUT_MSB SC_NLINE_SKIP SC_SAMPLE_BUFFILL SC_MAX_BUFFILL_P_0 SC_MAX_BUFFILL_P_1 SC_MAX_BUFFILL_D_0 SC_MAX_BUFFILL_D_1 SC_SAMPLE_FIFOFILL SC_MAX_FIFOFILL_PI SC_MIN_FIFOFILL_PO1 SC_MIN_FIFOFILL_PO2 SC_MIN_FIFOFILL_PO3 SC_MIN_FIFOFILL_PO4 SC_MAX_FIFOFILL_DI SC_MAX_FIFOFILL_DO SC_VS_LUT_0 SC_VS_LUT_1 SC_VS_LUT_2 SC_VS_LUT_3
DELTA_PHASE_V[6:0] DELTA_PHASE_H[4:0] START_PHASE_H[3:0]
SAMPLE_BUFFILL_COMMAND[7:0] MAX_BUFFILL_P[7:0] x MAX_BUFFILL_D[7:0] x SAMPLE_FIFOFILL_COMMAND[7:0]
150 MHz pixel rate HDMI transmitter
TDA9983B
44 of 119
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Table 51. Register SC_VS_LUT_4 SC_VS_LUT_5 SC_VS_LUT_6 SC_VS_LUT_7 SC_VS_LUT_8 SC_VS_LUT_9 SC_VS_LUT_10 SC_VS_LUT_11 SC_VS_LUT_12 SC_VS_LUT_13 SC_VS_LUT_14 SC_VS_LUT_15
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 01h[1] ...continued Sub R/W addr 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) VS_LUT4[7:0] VS_LUT5[7:0] VS_LUT6[7:0] VS_LUT7[7:0] VS_LUT8[7:0] VS_LUT9[7:0] VS_LUT10[7:0] VS_LUT11[7:0] VS_LUT12[7:0] VS_LUT13[7:0] VS_LUT14[7:0] VS_LUT15[7:0] VS_LUT16[7:0] VS_LUT17[7:0] VS_LUT18[7:0] VS_LUT19[7:0] VS_LUT20[7:0] VS_LUT21[7:0] VS_LUT22[7:0] VS_LUT23[7:0] VS_LUT24[7:0] VS_LUT25[7:0] VS_LUT26[7:0] VS_LUT27[7:0] VS_LUT28[7:0] VS_LUT29[7:0] VS_LUT30[7:0] VS_LUT31[7:0] VS_LUT32[7:0] VS_LUT33[7:0] VS_LUT34[7:0] VS_LUT35[7:0] Default value XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
Product data sheet 45 of 119
TDA9983B_1
NXP Semiconductors
SC_VS_LUT_16 SC_VS_LUT_17 SC_VS_LUT_18 SC_VS_LUT_19 SC_VS_LUT_20 SC_VS_LUT_21 SC_VS_LUT_22 SC_VS_LUT_23 SC_VS_LUT_24 SC_VS_LUT_25 SC_VS_LUT_26 SC_VS_LUT_27 SC_VS_LUT_28 SC_VS_LUT_29 SC_VS_LUT_30 SC_VS_LUT_31 SC_VS_LUT_32 SC_VS_LUT_33 SC_VS_LUT_34 SC_VS_LUT_35
150 MHz pixel rate HDMI transmitter
TDA9983B
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Table 51. Register SC_VS_LUT_36 SC_VS_LUT_37 SC_VS_LUT_38 SC_VS_LUT_39 SC_VS_LUT_40 SC_VS_LUT_41 SC_VS_LUT_42 SC_VS_LUT_43 SC_VS_LUT_44 Not used : Not used
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 01h[1] ...continued Sub R/W addr 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h : 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h : BCh BDh BEh BFh C0h C1h C2h C3h C4h W W W W W W W W W : W W W W W W W W W : W W W W W W W W x x x x x x x x x x x x x x x x x x x x NLINE[7:0] : x x x x x x x x VWIN_START_1[9:8] VWIN_END_1[9:8] VWIN_START_2[9:8] VWIN_END_2[9:8] VWIN_START_1[7:0] VWIN_END_1[7:0] VWIN_START_2[7:0] VWIN_END_2[7:0] x x x x x x x x x x x x x x x x NPIX[7:0] x x NLINE[9:8] Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) VS_LUT36[7:0] VS_LUT37[7:0] VS_LUT38[7:0] VS_LUT39[7:0] VS_LUT40[7:0] VS_LUT41[7:0] VS_LUT42[7:0] VS_LUT43[7:0] VS_LUT44[7:0] : x x x x x x x VIDFORMAT[2:0] PRESET_PIX[9:8] PRESET_LINE[9:8] NPIX[9:8] Default value XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000 : 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Product data sheet 46 of 119
TDA9983B_1
NXP Semiconductors
VIDFORMAT REFPIX_MSB REFPIX_LSB REFLINE_MSB REFLINE_LSB NPIX_MSB NPIX_LSB NLINE_MSB NLINE_LSB Not used : Not used VWIN_START_1_MSB VWIN_START_1_LSB VWIN_END_1_MSB VWIN_END_1_LSB VWIN_START_2_MSB VWIN_START_2_LSB VWIN_END_2_MSB VWIN_END_2_LSB
PRESET_PIX[7:0] PRESET_LINE[7:0]
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 51. Register DE_START_MSB DE_START_LSB DE_STOP_MSB DE_STOP_LSB Not used TBG_CNTRL_0 Not used : Not used CURPAGE_ADR
[1] R: reading register W: writing register x: bit must be set to default value for proper operation -: not used Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 01h[1] ...continued Sub R/W addr C5h C6h C7h C8h C9h CAh CBh : FEh FFh W W W W W : W SYNC_ ONCE SYNC_ MTHD FRAME_ DIS x x x Bit 7 (MSB) x 6 x 5 x 4 x x x : CURPAGE_ADR[7:0] 3 x x TOP_EXT 2 x x DE_EXT 1 0 (LSB) DE_START[9:8] DE_END[9:8] TOP_SEL TOP_TGL Default value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000
Product data sheet 47 of 119
TDA9983B_1
NXP Semiconductors
DE_START[7:0] DE_END[7:0]
150 MHz pixel rate HDMI transmitter
TDA9983B
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.4.1 Scaler control registers
Table 52. SC_VIDFORMAT register (address 00h) bit description Legend: * = default value Bit Symbol Access Value Description W 00* 01 1X 5 to 3 VID_FORMAT_O[2:0] W 000* 001 010 011 1XX 2 to 0 VID_FORMAT_I[2:0] W 000* 001 010 011 1XX look-up table select default coefficient set #1 (video) default coefficient set #2 (enhanced sharpness) coefficient set as programmed via I2C-bus video format output 480p 60 Hz 576p 50 Hz 720p 50 Hz/60 Hz 1080i 50 Hz/60 Hz customized format video format input 480i 60 Hz 576i 50 Hz 480p 60 Hz 576p 50 Hz customized format 7 and 6 LUT_SEL[1:0]
Table 53. SC_CNTRL register (address 01h) bit description Legend: * = default value Bit 7 to 4 3 Symbol x IL_OUT_ON Access Value Description W W 0* 1 2 PHASES_V W 0* 1 1 VS_ON W 0* 1 0 DEIL_ON W 0* 1 0000* undefined interlaced output on internal line phase toggle is ignored interlaced output; output lines depend on internal line phase toggle vertical phases 90 vertical phases 54 vertical phases vertical scaler on vertical scaler off vertical scaler on deinterlacer on deinterlacer off deinterlacer on
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
48 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 54. SC_x_PHASE_x registers (address 02h to 04h) bit description Legend: * = default value Address 02h 03h 04h Register SC_DELTA_PHASE_V SC_DELTA_PHASE_H SC_START_PHASE_H Bit 7 6 to 0 7 to 5 4 to 0 7 to 4 3 to 0 Symbol x DELTA_PHASE_V[6:0] x DELTA_PHASE_H[4:0] x START_PHASE_H[3:0] Access Value W W W W W W 0* 001 1110* 000* 1 0000* 0000* 0000* Description undefined delta phase vertical undefined delta phase horizontal undefined start phase horizontal
Table 55. SC_NPIX_xx registers (address 05h to 08h) bit description Legend: * = default value Address 06h 05h 08h 07h Register SC_NPIX_IN_MSB SC_NPIX_IN_LSB SC_NPIX_OUT_MSB SC_NPIX_OUT_LSB Bit 7 to 2 1 to 0 7 to 0 7 to 3 2 to 0 7 to 0 Symbol x NPIX_IN[9:8] NPIX_IN[7:0] x NPIX_OUT[10:8] NPIX_OUT[7:0] Access Value W W W W W W 0000 00* 10* D0h* 0000 0* 010* D0h* undefined number of output pixels Description undefined number of input pixels
Table 56. SC_NLINE_xx registers (address 09h to 0Dh) bit description Legend: * = default value Address 0Ah 09h 0Ch 0Bh 0Dh Register SC_NLINE_IN_MSB SC_NLINE_IN_LSB SC_NLINE_OUT_MSB SC_NLINE_OUT_LSB SC_NLINE_SKIP Bit 7 to 2 1 to 0 7 to 0 7 to 2 1 to 0 7 to 0 7 to 3 2 to 0 Symbol x NLINE_IN[9:8] NLINE_IN[7:0] x NLINE_OUT[9:8] NLINE_OUT[7:0] x NLINE_SKIP[2:0] Access Value W W W W W W W W 0000 00* 10* 40h* 0000 00* 10* 40h* 0000 0* 000* undefined number of output lines skipped: by vertical scaler undefined number of output lines Description undefined number of input lines
Table 57. SC_x_BUFFILL_xx registers (address 0Eh to 12h) bit description Legend: * = default value Address 0Eh Register SC_SAMPLE_BUFFILL Bit 7 to 0 Symbol SAMPLE_BUFFILL_ COMMAND[7:0] Access Value Description R sample buffer filling command: when this address is read the BUFFILL values are sampled undefined max buffer filling primary: filling primary video buffer
10h 0Fh
SC_MAX_BUFFILL_P_1 SC_MAX_BUFFILL_P_0
7 to 4 3 to 0 7 to 0
x MAX_BUFFILL_P[11:8] MAX_BUFFILL_P[7:0]
R R R
-
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150 MHz pixel rate HDMI transmitter
Table 57. SC_x_BUFFILL_xx registers (address 0Eh to 12h) bit description ...continued Legend: * = default value Address 12h 11h Register SC_MAX_BUFFILL_D_1 SC_MAX_BUFFILL_D_0 Bit 7 to 4 3 to 0 7 to 0 Symbol x MAX_BUFFILL_D[11:8] MAX_BUFFILL_D[7:0] Access Value Description R R R undefined max buffer filling deinterlaced: filling video deinterlaced buffer
Table 58. SC_xx_FIFOFILL_xx registers (address 13h to 1Ah) bit description Legend: * = default value Address Register 13h SC_SAMPLE_FIFOFILL Bit Symbol Access Value Description R sample FIFO filling command: when this address is read the FIFOFILL values are sampled undefined max FIFO filling primary input: filling primary video input FIFO undefined min FIFO filling primary output 1: filling primary video output FIFO#1 undefined min FIFO filling primary output 2: filling primary video output FIFO#2 undefined min FIFO filling primary output 3: filling primary video output FIFO#3 undefined min FIFO filling primary output 4: filling primary video output FIFO#4 undefined max FIFO filling deinterlaced input: filling deinterlaced video input FIFO undefined max FIFO filling deinterlaced output: filling deinterlaced video output FIFO 7 to 0 SAMPLE_FIFOFILL_ COMMAND[7:0] 7 to 5 x 4 to 0 MAX_FIFOFILL_PI[4:0] 15h SC_MIN_FIFOFILL_PO1 7 to 5 x
14h
SC_MAX_FIFOFILL_PI
R R R
-
4 to 0 MIN_FIFOFILL_PO1[4:0] R
16h
SC_MIN_FIFOFILL_PO2 7 to 5 x
R
-
4 to 0 MIN_FIFOFILL_PO2[4:0] R
17h
SC_MIN_FIFOFILL_PO3 7 to 5 x
R
-
4 to 0 MIN_FIFOFILL_PO3[4:0] R
18h
SC_MIN_FIFOFILL_PO4 7 to 5 x
R
-
4 to 0 MIN_FIFOFILL_PO4[4:0] R
19h
SC_MAX_FIFOFILL_DI
7 to 5 x 4 to 0 MAX_FIFOFILL_DI[4:0]
R R
-
1Ah
SC_MAX_FIFOFILL_DO 7 to 5 x
R
-
4 to 0 MAX_FIFOFILL_DO[4:0] R
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description Legend: * = default value Address Register 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h SC_VS_LUT_0 SC_VS_LUT_1 SC_VS_LUT_2 SC_VS_LUT_3 SC_VS_LUT_4 SC_VS_LUT_5 SC_VS_LUT_6 SC_VS_LUT_7 SC_VS_LUT_8 SC_VS_LUT_9 SC_VS_LUT_10 SC_VS_LUT_11 SC_VS_LUT_12 SC_VS_LUT_13 SC_VS_LUT_14 SC_VS_LUT_15 SC_VS_LUT_16 SC_VS_LUT_17 SC_VS_LUT_18 SC_VS_LUT_19 SC_VS_LUT_20 SC_VS_LUT_21 SC_VS_LUT_22 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol VS_LUT0[7:0] VS_LUT1[7:0] VS_LUT2[7:0] VS_LUT3[7:0] VS_LUT4[7:0] VS_LUT5[7:0] VS_LUT6[7:0] VS_LUT7[7:0] VS_LUT8[7:0] VS_LUT9[7:0] VS_LUT10[7:0] VS_LUT11[7:0] VS_LUT12[7:0] VS_LUT13[7:0] VS_LUT14[7:0] VS_LUT15[7:0] VS_LUT16[7:0] VS_LUT17[7:0] VS_LUT18[7:0] VS_LUT19[7:0] VS_LUT20[7:0] VS_LUT21[7:0] VS_LUT22[7:0] Access Value Description W W W W W W W W W W W W W W W W W W W W W W W vertical scaler LUT 0: external LUT coefficient[0] for vertical scaler vertical scaler LUT 1: external LUT coefficient[1] for vertical scaler vertical scaler LUT 2: external LUT coefficient[2] for vertical scaler vertical scaler LUT 3: external LUT coefficient[3] for vertical scaler vertical scaler LUT 4: external LUT coefficient[4] for vertical scaler vertical scaler LUT 5: external LUT coefficient[5] for vertical scaler vertical scaler LUT 6: external LUT coefficient[6] for vertical scaler vertical scaler LUT 7: external LUT coefficient[7] for vertical scaler vertical scaler LUT 8: external LUT coefficient[8] for vertical scaler vertical scaler LUT 9: external LUT coefficient[9] for vertical scaler vertical scaler LUT 10: external LUT coefficient[10] for vertical scaler vertical scaler LUT 11: external LUT coefficient[11] for vertical scaler vertical scaler LUT 12: external LUT coefficient[12] for vertical scaler vertical scaler LUT 13: external LUT coefficient[13] for vertical scaler vertical scaler LUT 14: external LUT coefficient[14] for vertical scaler vertical scaler LUT 15: external LUT coefficient[15] for vertical scaler vertical scaler LUT 16: external LUT coefficient[16] for vertical scaler vertical scaler LUT 17: external LUT coefficient[17] for vertical scaler vertical scaler LUT 18: external LUT coefficient[18] for vertical scaler vertical scaler LUT 19: external LUT coefficient[19] for vertical scaler vertical scaler LUT 20: external LUT coefficient[20] for vertical scaler vertical scaler LUT 21: external LUT coefficient[21] for vertical scaler vertical scaler LUT 22: external LUT coefficient[22] for vertical scaler
(c) NXP B.V. 2008. All rights reserved.
TDA9983B_1
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 59. SC_VS_LUT_xx registers (address 1Bh to 47h) bit description ...continued Legend: * = default value Address Register 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h SC_VS_LUT_23 SC_VS_LUT_24 SC_VS_LUT_25 SC_VS_LUT_26 SC_VS_LUT_27 SC_VS_LUT_28 SC_VS_LUT_29 SC_VS_LUT_30 SC_VS_LUT_31 SC_VS_LUT_32 SC_VS_LUT_33 SC_VS_LUT_34 SC_VS_LUT_35 SC_VS_LUT_36 SC_VS_LUT_37 SC_VS_LUT_38 SC_VS_LUT_39 SC_VS_LUT_40 SC_VS_LUT_41 SC_VS_LUT_42 SC_VS_LUT_43 SC_VS_LUT_44 Bit 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 Symbol VS_LUT23[7:0] VS_LUT24[7:0] VS_LUT25[7:0] VS_LUT26[7:0] VS_LUT27[7:0] VS_LUT28[7:0] VS_LUT29[7:0] VS_LUT30[7:0] VS_LUT31[7:0] VS_LUT32[7:0] VS_LUT33[7:0] VS_LUT34[7:0] VS_LUT35[7:0] VS_LUT36[7:0] VS_LUT37[7:0] VS_LUT38[7:0] VS_LUT39[7:0] VS_LUT40[7:0] VS_LUT41[7:0] VS_LUT42[7:0] VS_LUT43[7:0] VS_LUT44[7:0] Access Value Description W W W W W W W W W W W W W W W W W W W W W W vertical scaler LUT 23: external LUT coefficient[23] for vertical scaler vertical scaler LUT 24: external LUT coefficient[24] for vertical scaler vertical scaler LUT 25: external LUT coefficient[25] for vertical scaler vertical scaler LUT 26: external LUT coefficient[26] for vertical scaler vertical scaler LUT 27: external LUT coefficient[27] for vertical scaler vertical scaler LUT 28: external LUT coefficient[28] for vertical scaler vertical scaler LUT 29: external LUT coefficient[29] for vertical scaler vertical scaler LUT 30: external LUT coefficient[30] for vertical scaler vertical scaler LUT 31: external LUT coefficient[31] for vertical scaler vertical scaler LUT 32: external LUT coefficient[32] for vertical scaler vertical scaler LUT 33: external LUT coefficient[33] for vertical scaler vertical scaler LUT 34: external LUT coefficient[34] for vertical scaler vertical scaler LUT 35: external LUT coefficient[35] for vertical scaler vertical scaler LUT 36: external LUT coefficient[36] for vertical scaler vertical scaler LUT 37: external LUT coefficient[37] for vertical scaler vertical scaler LUT 38: external LUT coefficient[38] for vertical scaler vertical scaler LUT 39: external LUT coefficient[39] for vertical scaler vertical scaler LUT 40: external LUT coefficient[40] for vertical scaler vertical scaler LUT 41: external LUT coefficient[41] for vertical scaler vertical scaler LUT 42: external LUT coefficient[42] for vertical scaler vertical scaler LUT 43: external LUT coefficient[43] for vertical scaler vertical scaler LUT 44: external LUT coefficient[44] for vertical scaler
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Product data sheet
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TDA9983B
150 MHz pixel rate HDMI transmitter
9.4.2 Scaling input time base generator control registers
Table 60. VIDFORMAT register (address A0h) bit description Legend: * = default value Bit 7 to 3 2 to 0 Symbol x VIDFORMAT[2:0] Access Value W W 000* 001 010 011 1XX Description video format: time base generator for scaler input formats 480i 60 Hz 576i 50 Hz 480p 60 Hz 576p 50 Hz reserved for future use 0000 0* undefined
Table 61. REFPIX_xx, REFLINE_xx, NPIX_xx and NLINE_xx registers (address A1h to A8h) bit description Legend: * = default value Address Register A1h A2h A3h A4h A5h A6h A7h A8h REFPIX_MSB REFPIX_LSB REFLINE_MSB REFLINE_LSB NPIX_MSB NPIX_LSB NLINE_MSB NLINE_LSB Bit Symbol Access Value W W W W W W W W W W W W 00* 01h* 00* 01h* 0000 00* undefined 00* 00h* 00* 00h* number pixel: number of pixels per line Description preset pixel: reference pixel preset 7 to 2 x 1 to 0 PRESET_PIX[9:8] 7 to 0 PRESET_PIX[7:0] 7 to 2 x 1 to 0 PRESET_LINE[9:8] 7 to 0 PRESET_LINE[7:0] 7 to 2 x 1 to 0 NPIX[9:8] 7 to 0 NPIX[7:0] 7 to 2 x 1 to 0 NLINE[9:8] 7 to 0 NLINE[7:0] 0000 00* undefined
0000 00* undefined preset line: reference line preset
0000 00* undefined number line: number of lines per frame
Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description Legend: * = default value Address Register BDh BEh BFh C0h C1h C2h VWIN_START_1_MSB VWIN_START_1_LSB VWIN_END_1_MSB VWIN_END_1_LSB VWIN_START_2_MSB VWIN_START_2_LSB Bit Symbol Access Value W W W W W W W W W 00* 00h* Description vertical window start 1: vertical window line number for start pulse in field 1 vertical window end 1: vertical window line number for end pulse in field 1 vertical window start 2: vertical window line number for start pulse in field 2 7 to 2 x 1 to 0 VWIN_START_1[9:8] 7 to 0 VWIN_START_1[7:0] 7 to 2 x 1 to 0 VWIN_END_1[9:8] 7 to 0 VWIN_END_1[7:0] 7 to 2 x 1 to 0 VWIN_START_2[9:8] 7 to 0 VWIN_START_2[7:0] 0000 00* undefined
0000 00* undefined 00* 00h*
0000 00* undefined 00* 00h*
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Product data sheet
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 62. VWIN_START_x_xx and VWIN_END_x_xx registers (address BDh to C4h) bit description ...continued Legend: * = default value Address Register C3h C4h VWIN_END_2_MSB VWIN_END_2_LSB Bit Symbol Access Value W W W 00* 00h* Description vertical window end 2: vertical window line number for end pulse in field 2 7 to 2 x 1 to 0 VWIN_END_2[9:8] 7 to 0 VWIN_END_2[7:0] 0000 00* undefined
Table 63. DE_START_x and DE_STOP_x registers (address C5h to C8h) bit description Legend: * = default value Address Register C5h C6h C7h C8h DE_START_MSB DE_START_LSB DE_STOP_MSB DE_STOP_LSB Bit Symbol Access Value W W W W W W 00* 00h* Description data enable start: data enable pixel number for start pulse in field 1 data enable end: data enable pixel number for end pulse in field 2 7 to 2 x 1 to 0 DE_START[9:8] 7 to 0 DE_START[7:0] 7 to 2 x 1 to 0 DE_END[9:8] 7 to 0 DE_END[7:0] 0000 00* undefined
0000 00* undefined 00* 00h*
Table 64. TBG_CNTRL_0 register (address CAh) bit description Legend: * = default value Bit 7 Symbol SYNC_ONCE Access Value W 0* 1 6 SYNC_MTHD W 0* 1 5 FRAME_DIS W 0* 1 4 3 x TOP_EXT W W 0* 1 2 DE_EXT W 0* 1 0* Description sync once line/pixel counters are synchronized each frame line/pixel counters are synchronized only once sync method synchronization is based on combination of v and h synchronization is based on combination of v and x (de) frame disable: synchronized by linecnt = 1 AND pixelcnt = 1 enable video frames disable video frames undefined top external top = top_tbg_sci top = x_vip (external; fref) data enable external de = de_tbg_sci (internal) de = x_vip (external; de)
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Product data sheet
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 64. TBG_CNTRL_0 register (address CAh) bit description ...continued Legend: * = default value Bit 1 Symbol TOP_SEL Access Value W 0* 1 0 TOP_TGL W 0* 1 Description top select top_tbg_sci = top_tbg_sci (internal; programmed via I2C-bus) top_tbg_sci = top_tbg_vrf top toggle no specific action toggle top_tbg_sci
9.4.3 Current page address register
Table 65. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol Access Value 00h* Description current page address: selects the current memory page CURPAGE_ADR[7:0] W
9.5 PLL settings page register definitions
The current page address for the PLL settings page is 02h. The configuration of the registers for this page is given in Table 66.
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Product data sheet Rev. 01 -- 20 May 2008
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NXP Semiconductors
Table 66. Register
I2C-bus registers of memory page 02h[1] Sub R/W addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h : FEh FFh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W : W x BYPASS_ PLLDE x x x x x x x x x PLLDE_HVP x x x x x x x x x x BYPASS_ SCG x Bit 7 (MSB) x 6 SRL_MAN_IP SRL_PR[3:0] x x SRL_PXIN_ SEL x x SELPLLCL KIN x x 5 4 SRL_REG_IP[2:0] x x x x 3 2 1 SRL_IZ[1:0] SRL_DE 0 (LSB) SRL_FDN SRL_CCIR Default value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 1001 0000 1111 1010 SCG_NDIV[10:8] x x SCG_ RDIV[8] PLLDE_ FDN REFDIV2 PLLSRL_ LOCK TST_HVP DIVTESTOE SEL_CLK1 0000 0000 0101 1011 0000 0000 1000 0001 0000 0001 0000 0000 0000 0011 0000 0000 SCG_FDN
PLL_SERIAL_1 PLL_SERIAL_2 PLL_SERIAL_3 SERIALIZER BUFFER_OUT PLL_SCG1 PLL_SCG2 PLL_SCGN1 PLL_SCGN2 PLL_SCGR1 PLL_SCGR2 PLL_DE CCIR_DIV VAI_PLL AUDIO_DIV TEST1 TEST2 SEL_CLK Not used : Not used CURPAGE_ADR
[1]
SRL_NOSC[1:0]
SRL_PHASE3[3:0] x x x x x x x x
SRL_PHASE2[3:0] SRL_FORCE[1:0] x x SRL_CLK[1:0] x SCG_NOSC[1:0]
SCG_NDIV[7:0] x x x x x x x x ENA_SC_ CLK : CURPAGE_ADR[7:0] x x SCG_RDIV[7:0]
PLLDE_NOSC[1:0] x PLLSCG_ HVP x x x x x PLLSRL_ HVP x TSTSER PHOE x x
PLLDE_IZ[1:0] x PLLDE_ LOCK x PLLSCG_ LOCK AUDIO_DIV[2:0] TST_NOSC PWD1V8
150 MHz pixel rate HDMI transmitter
0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000
SEL_VRF_CLK[1:0]
TDA9983B
R: reading register W: writing register x: bit must be set to default value for proper operation -: not used
56 of 119
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TDA9983B
150 MHz pixel rate HDMI transmitter
9.5.1 PLL serial registers
Table 67. PLL_SERIAL_1 register (address 00h) bit description Legend: * = default value Bit 7 6 Symbol x SRL_MAN_IP Access Value R/W R/W 0* 1 5 to 3 SRL_REG_IP[2:0] R/W 000* 001 010 011 100 101 110 111 2 to 1 SRL_IZ[1:0] R/W 00* 01 10 11 0 SRL_FDN R/W 0* 1 0* Description undefined serializer manual current pole automatic setting of output current pole charge pump (ip_auto) manual setting of output current pole charge pump (ip_manual) serializer current pole: PLL pole charge pump output current (ip_manual) 400 nA 200 nA 133 nA 100 nA 80 nA 66 nA 57 nA 50 nA serializer zero current: PLL zero charge pump output current Iz / 5 Iz / 10 Iz / 15 Iz / 20 serializer fdn normal (PLL loop active) standby (PLL loop open)
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 68. PLL_SERIAL_2 register (address 01h) bit description Legend: * = default value Bit 7 to 4 Symbol SRL_PR[3:0] Access Value R/W 0000* 0001 0010 0011 0100 0101 0110 0111 1000 1001 other 3 to 2 1 to 0 x SRL_NOSC[1:0] R/W R/W 00* 01 10 11 00* Description serializer pixel repetition: pixel repetition factor (ip_auto) pr = 1 (ip_auto = 400 nA) pr = 2 (ip_auto = 200 nA) pr = 3 (ip_auto = 133 nA) pr = 4 (ip_auto = 100 nA) pr = 5 (ip_auto = 80 nA) pr = 6 (ip_auto = 66 nA) pr = 7 (ip_auto = 57 nA) pr = 8 (ip_auto = 50 nA) pr = 9 (ip_auto = 50 nA) pr = 10 (ip_auto = 50 nA) undefined undefined serializer N oscillator: predivider division factor div_by_1; PLL output frequency range = (800 to 1500) Msample/s (Iz = 1.0+) div_by_2; PLL output frequency range = (400 to 800) Msample/s (Iz = 1.5+) div_by_4; PLL output frequency range = (200 to 400) Msample/s (Iz = 2.0+) div_by_4; PLL output frequency range = (200 to 400) Msample/s (Iz = 2.0+)
Table 69. PLL_SERIAL_3 register (address 02h) bit description Legend: * = default value Bit 7 to 5 4 Symbol x SRL_PXIN_SEL Access Value R/W R/W 0* 1 3 to 2 1 x SRL_DE R/W R/W 0* 1 0 SRL_CCIR R/W 0* 1 00* 000* Description undefined serializer pixel input select PXINclko = SCAclko PXINclko = SCAclko / 2 undefined serializer double edge: double edge divider in feedback loop no division divide by 2 serializer CCIR pllsrl_in = pllsrl_refin pllsrl_in = pllsrl_refin / 2
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 70. SERIALIZER register (address 03h) bit description Legend: * = default value Bit 7 to 4 3 to 0 Symbol SRL_PHASE3[3:0] SRL_PHASE2[3:0] Access Value R/W R/W 0000* 0000* Description serializer phase 3: phase selection of third storage level of the serializer input serializer phase 2: phase selection of second storage level of the serializer input
Table 71. BUFFER_OUT register (address 04h) bit description Legend: * = default value Bit 7 to 4 3 to 2 Symbol x SRL_FORCE[1:0] Access Value R/W R/W 00* 01 10 11 1 to 0 SRL_CLK[1:0] R/W 00* 01 10 11 0000* Description undefined serializer force TMDS outputs active (normal operation) TMDS outputs active (normal operation) TMDS outputs forced '0' TMDS outputs forced '1' serializer clock TMDS TXC = TMDSclk (normal operation) TMDS TXC = SERclk / 2 TMDS TXC = undefined TMDS TXC = SERclk
Table 72. PLL_SCG1 register (address 05h) bit description Legend: * = default value Bit 7 to 1 0 Symbol x SCG_FDN Access Value R/W R/W 0 1* 0000 000* Description undefined scg fnd normal (PLL loop active) standby (PLL loop open)
Table 73. PLL_SCG2 register (address 06h) bit description Legend: * = default value Bit 7 Symbol BYPASS_SCG Access Value R/W 0 1* 6 to 5 4 x SELPLLCLKIN R/W R/W 0 1* 3 to 2 x R/W 00* 00* Description bypass scg SCAclko = scg_nosc predivider output SCAclko = pllscg_inref undefined select PLL clock input pllscg_in = pllsca_inref pllscg_in = pllclkin undefined
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Product data sheet
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 73. PLL_SCG2 register (address 06h) bit description ...continued Legend: * = default value Bit 1 to 0 Symbol SCG_NOSC[1:0] Access Value R/W 00* 01 10 11 Description scg N oscillator div_by_1; PLL output frequency range = (80 to 150) Msample/s div_by_2; PLL output frequency range = (40 to 80) Msample/s div_by_4; PLL output frequency range = (20 to 40) Msample/s div_by_8; PLL output frequency range = (10 to 20) Msample/s
Table 74. PLL_SCGNx registers (address 07h to 08h) bit description Legend: * = default value Address Register 08h 07h PLL_SCGN2 PLL_SCGN1 Bit Symbol Access Value R/W R/W R/W 0000 0* 000* FAh* Description undefined scg N divider: PLL feedback oscillator divider 7 to 3 x 2 to 0 SCG_NDIV[10:8] 7 to 0 SCG_NDIV[7:0]
Table 75. PLL_SCGRx registers (address 09h to 0Ah) bit description Legend: * = default value Address Register 0Ah 09h PLL_SCGR2 PLL_SCGR1 Bit 0 Symbol SCG_RDIV[8] Access Value R/W R/W R/W 0* 5Bh* Description scg R divider: divider value of the PLL reference input clock 7 to 1 x 7 to 0 SCG_RDIV[7:0] 0000 000* undefined
Table 76. PLL_DE register (address 0Bh) bit description Legend: * = default value Bit 7 Symbol BYPASS_PLLDE Access Value R/W 0 1* 6 5 to 4 x PLLDE_NOSC[1:0] R/W R/W 00* 01 10 11 3 x R/W 0* 0* Description bypass PLL double edge pllde0 = de_nosc predivider output pllde0 = pllde_inref undefined PLL double edge N oscillator div_by_1; PLL output frequency range = (80 to 150) Msample/s div_by_2; PLL output frequency range = (40 to 80) Msample/s div_by_4; PLL output frequency range = (20 to 40) Msample/s div_by_8; PLL output frequency range = (10 to 20) Msample/s undefined
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Product data sheet
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 76. PLL_DE register (address 0Bh) bit description ...continued Legend: * = default value Bit 2 to 1 Symbol PLLDE_IZ[1:0] Access Value R/W 00* 01 10 11 0 PLLDE_FDN R/W 0 1* Description PLL double edge zero current Iz / 5 Iz / 10 Iz / 15 Iz / 20 PLL double edge fdn normal (PLL loop active) standby (PLL loop open)
Table 77. CCIR_DIV register (address 0Ch) bit description Legend: * = default value Bit 7 to 1 0 Symbol x REFDIV2 Access Value R/W R/W 0 1* 0000 000* Description undefined reference divider 2 pllde_inref = pllclkin pllde_inref = pllclkin / 2
Table 78. VAI_PLL register (address 0Dh) bit description Legend: * = default value Bit 7 6 Symbol x PLLDE_HVP Access Value Description R R 0* 1 5 PLLSCG_HVP R 0* 1 4 PLLSRL_HVP R 0* 1 3 2 x PLLDE_LOCK R R 0* 1 1 PLLSCG_LOCK R 0* 1 0 PLLSRL_LOCK R 0* 1
TDA9983B_1
0*
undefined PLL DE high voltage protection PLLDE high voltage protection cell output is '0' PLLDE high voltage protection cell output is '1' PLL SCG high voltage protection PLLSCG high voltage protection cell output is '0' PLLSCG high voltage protection cell output is '1' PLL SRL high voltage protection PLLSRL high voltage protection cell output is '0' PLLSRL high voltage protection cell output is '1' undefined PLL DE locked PLLDE not locked PLLDE in lock PLL SCG locked PLLSCG not locked PLLSCG in lock PLL SRL locked PLLSRL not locked PLLSRL in lock
(c) NXP B.V. 2008. All rights reserved.
0*
Product data sheet
Rev. 01 -- 20 May 2008
61 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 79. AUDIO_DIV register (address 0Eh) bit description Legend: * = default value Bit 7 to 3 2 to 0 Symbol x AUDIO_DIV[2:0] Access Value R/W R/W 000 001 010 011* 100 101 11X Table 80. TESTx registers (address 0Fh and 10h) bit description Legend: * = default value Address Register 0Fh TEST1 Bit 4 Symbol TSTSERPHOE Access Value R/W R/W 0* 1 3 to 2 x 1 TST_NOSC R/W R/W 0* 1 0 TST_HVP R/W 0* 1 10h TEST2 7 to 2 x 1 PWD1V8 R/W R/W 0* 1 0 DIVTESTOE R/W 0* 1 00* 000* Description undefined test serializer phoe srl_tst_ph2_o = '0'; srl_tst_ph3_o = '0' srl_tst_ph2_o = 'active'; srl_tst_ph3_o = 'active' undefined test N oscillator: test mode nosc predividers normal mode; input nosc predivider = PLL oscillator output test mode; input nosc predivider = PLL reference input test high voltage protection: test high voltage protection cells normal PLL mode test mode; HVP input forced to VDDA(PLL_3V3) power-down 1.8 V normal operation sleep mode PLLs divider tests output enable: enable activity of scaler PLL dividers test outputs test outputs = '0' test outputs = active 7 to 5 x Description audio divider: not guaranteed; under reservation (ip_manual) Audio_Clk_Out = SERclk / 1 Audio_Clk_Out = SERclk / 2 Audio_Clk_Out = SERclk / 4 Audio_Clk_Out = SERclk / 8 Audio_Clk_Out = SERclk / 16 Audio_Clk_Out = SERclk / 32 do not use 0000 0* undefined
0000 00* undefined
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
62 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 81. SEL_CLK register (address 11h) bit description Legend: * = default value Bit 7 to 4 3 Symbol x ENA_SC_CLK Access Value R/W R/W 0* 1 2 to 1 SEL_VRF_CLK[1:0] R/W 00* 01 10 11 0 SEL_CLK1 R/W 0* 1 0000* Description undefined enable scaler clocks disable scaler clocks (sc_clk_m, clk1_m) enable scaler clocks (sc_clk_m, clk1_m) select video reformatter clock vrf_clk_m = not tmdsclkpo; sc_clk_m = tmdsclkpo vrf_clk_m = scaclko_pllscgon; sc_clk_m = not scaclko_pllscgon vrf_clk_m = scaclko_tmdsclkn; sc_clk_m = not scaclko_tmdsclkn vrf_clk_m = scaclko_tmdsclkn; sc_clk_m = not scaclko_tmdsclkn select clock 1 clk1_m = not (plldeo) clk1_m = plldeo_div2
9.5.2 Current page address register
Table 82. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol Access Value 00h* Description current page address: selects the current memory page CURPAGE_ADR[7:0] W
9.6 Information frames and packets page register definitions
The current page address for the Information frames and packets page is 10h. The configuration of the registers for this page is given in Table 83.
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
63 of 119
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Product data sheet Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved. TDA9983B_1
NXP Semiconductors
Table 83. Register Not used : Not used
I2C-bus registers of memory page 10h[1] Sub addr 00h : 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch R/W 7 (MSB) : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W x x x 6 5 4 : VSP_IF_TYPE[7:0] VSP_IF_VERSION[7:0] VSP_IF_LENGTH[4:0] VSP_IF_CHECKSUM[7:0] VSP_IF_IEEE[7:0] VSP_IF_IEEE[15:8] VSP_IF_IEEE[23:16] VSP_IF_PB4[7:0] VSP_IF_PB5[7:0] VSP_IF_PB6[7:0] VSP_IF_PB7[7:0] VSP_IF_PB8[7:0] VSP_IF_PB9[7:0] VSP_IF_PB10[7:0] VSP_IF_PB11[7:0] VSP_IF_PB12[7:0] VSP_IF_PB13[7:0] VSP_IF_PB14[7:0] VSP_IF_PB15[7:0] VSP_IF_PB16[7:0] VSP_IF_PB17[7:0] VSP_IF_PB18[7:0] VSP_IF_PB19[7:0] VSP_IF_PB20[7:0] VSP_IF_PB21[7:0] VSP_IF_PB22[7:0] VSP_IF_PB23[7:0] VSP_IF_PB24[7:0] VSP_IF_PB25[7:0] Bit 3 2 1 0 (LSB) 0000 0000 : 0000 0000 1000 0001 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Default value
VSP_IF_TYPE VSP_IF_VERSION VSP_IF_LENGTH VSP_IF_CHECKSUM VSP_IF_IEEE_LSB VSP_IF_IEEE_ISB VSP_IF_IEEE_MSB VSP_IF_BYTE4 VSP_IF_BYTE5 VSP_IF_BYTE6 VSP_IF_BYTE7 VSP_IF_BYTE8 VSP_IF_BYTE9 VSP_IF_BYTE10 VSP_IF_BYTE11 VSP_IF_BYTE12 VSP_IF_BYTE13 VSP_IF_BYTE14 VSP_IF_BYTE15 VSP_IF_BYTE16 VSP_IF_BYTE17 VSP_IF_BYTE18 VSP_IF_BYTE19 VSP_IF_BYTE20 VSP_IF_BYTE21 VSP_IF_BYTE22 VSP_IF_BYTE23 VSP_IF_BYTE24 VSP_IF_BYTE25
150 MHz pixel rate HDMI transmitter
TDA9983B
64 of 119
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Table 83. Register VSP_IF_BYTE26 VSP_IF_BYTE27 Not used AVI_IF_TYPE AVI_IF_VERSION AVI_IF_LENGTH AVI_IF_CHECKSUM AVI_IF_BYTE1 AVI_IF_BYTE2 AVI_IF_BYTE3 AVI_IF_BYTE4 AVI_IF_BYTE5
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 10h[1] ...continued Sub addr 3Dh 3Eh 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch R/W 7 (MSB) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W reserved reserved LINE_E_TP_BAR[7:0] LINE_E_TP_BAR[15:8] LINE_S_BT_BAR[7:0] LINE_S_BT_BAR[15:8] PIX_E_LF_BAR[7:0] PIX_E_LF_BAR[15:8] PIX_S_RG_BAR[7:0] PIX_S_RG_BAR[15:8] AVI_IF_RB14[7:0] AVI_IF_RB15[7:0] AVI_IF_RB16[7:0] AVI_IF_RB17[7:0] AVI_IF_RB18[7:0] AVI_IF_RB19[7:0] AVI_IF_RB20[7:0] AVI_IF_RB21[7:0] AVI_IF_RB22[7:0] AVI_IF_RB23[7:0] AVI_IF_RB24[7:0] AVI_IF_RB25[7:0] reserved AVI_IF_Y[1:0] AVI_IF_C[1:0] x x x AVI_IF_A reserved AVI_IF_VIC[6:0] AVI_IF_PR[3:0] 6 5 4 Bit 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0000 1000 0010 0000 0000 0000 0000 0000 0000 AVI_IF_S[1:0] AVI_IF_SC[1:0] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 AVI_IF_R[3:0] AVI_IF_LENGTH[4:0] AVI_IF_CHECKSUM[7:0] AVI_IF_B[1:0] AVI_IF_M[1:0] VSP_IF_PB26[7:0] VSP_IF_PB27[7:0] AVI_IF_TYPE[7:0] AVI_IF_VERSION[7:0] Default value
Product data sheet 65 of 119
TDA9983B_1
NXP Semiconductors
AVI_IF_BYTE6 AVI_IF_BYTE7 AVI_IF_BYTE8 AVI_IF_BYTE9 AVI_IF_BYTE10 AVI_IF_BYTE11 AVI_IF_BYTE12 AVI_IF_BYTE13 AVI_IF_BYTE14 AVI_IF_BYTE15 AVI_IF_BYTE16 AVI_IF_BYTE17 AVI_IF_BYTE18 AVI_IF_BYTE19 AVI_IF_BYTE20 AVI_IF_BYTE21 AVI_IF_BYTE22 AVI_IF_BYTE23 AVI_IF_BYTE24 AVI_IF_BYTE25
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 83. Register AVI_IF_BYTE26 AVI_IF_BYTE27 Not used SPD_IF_TYPE SPD_IF_VERSION SPD_IF_LENGTH SPD_IF_CHECKSUM SPD_IF_BYTE1 SPD_IF_BYTE2 SPD_IF_BYTE3 SPD_IF_BYTE4 SPD_IF_BYTE5
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 10h[1] ...continued Sub addr 5Dh 5Eh 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h 6Ah 6Bh 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh 7Ch R/W 7 (MSB) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x x x x x x x x x x x x x x x x x x x x 6 5 4 Bit 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0000 1000 0011 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 AVI_IF_RB26[7:0] AVI_IF_RB27[7:0] SPD_IF_TYPE[7:0] SPD_IF_VERSION[7:0] SPD_IF_LENGTH[4:0] SPD_IF_CHECKSUM[7:0] SPD_IF_VN1[6:0] SPD_IF_VN2[6:0] SPD_IF_VN3[6:0] SPD_IF_VN4[6:0] SPD_IF_VN5[6:0] SPD_IF_VN6[6:0] SPD_IF_VN7[6:0] SPD_IF_VN8[6:0] SPD_IF_PD1[6:0] SPD_IF_PD2[6:0] SPD_IF_PD3[6:0] SPD_IF_PD4[6:0] SPD_IF_PD5[6:0] SPD_IF_PD6[6:0] SPD_IF_PD7[6:0] SPD_IF_PD8[6:0] SPD_IF_PD9[6:0] SPD_IF_PD10[6:0] SPD_IF_PD11[6:0] SPD_IF_PD12[6:0] SPD_IF_PD13[6:0] SPD_IF_PD14[6:0] SPD_IF_PD15[6:0] SPD_IF_PD16[6:0] SPD_IF_SDI[7:0] Default value
Product data sheet 66 of 119
TDA9983B_1
NXP Semiconductors
SPD_IF_BYTE6 SPD_IF_BYTE7 SPD_IF_BYTE8 SPD_IF_BYTE9 SPD_IF_BYTE10 SPD_IF_BYTE11 SPD_IF_BYTE12 SPD_IF_BYTE13 SPD_IF_BYTE14 SPD_IF_BYTE15 SPD_IF_BYTE16 SPD_IF_BYTE17 SPD_IF_BYTE18 SPD_IF_BYTE19 SPD_IF_BYTE20 SPD_IF_BYTE21 SPD_IF_BYTE22 SPD_IF_BYTE23 SPD_IF_BYTE24 SPD_IF_BYTE25
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 83. Register SPD_IF_BYTE26 SPD_IF_BYTE27 Not used AUD_IF_TYPE AUD_IF_VERSION AUD_IF_LENGTH AUD_IF_CHECKSUM AUD_IF_BYTE1 AUD_IF_BYTE2 AUD_IF_BYTE3 AUD_IF_BYTE4 AUD_IF_BYTE5
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 10h[1] ...continued Sub addr 7Dh 7Eh 7Fh 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh R/W 7 (MSB) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W AUD_IF_ DM_INH AUD_IF_CT[3:0] reserved x x x 6 5 4 Bit 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0000 1000 0100 0000 0000 0000 0000 0000 0000 AUD_IF_CC[2:0] AUD_IF_SS[1:0] 0000 0000 0000 0000 0000 0000 0000 0000 reserved 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SPD_IF_BYTE26[7:0] SPD_IF_BYTE27[7:0] AUD_IF_TYPE[7:0] AUD_IF_VERSION[7:0] AUD_IF_LENGTH[4:0] AUD_IF_CHECKSUM[7:0] reserved AUD_IF_SF[2:0] AUD_IF_BYTE3[7:0] AUD_IF_CA[7:0] AUD_IF_LSV[3:0] AUD_IF_BYTE6[7:0] AUD_IF_BYTE7[7:0] AUD_IF_BYTE8[7:0] AUD_IF_BYTE9[7:0] AUD_IF_BYTE10[7:0] AUD_IF_BYTE11[7:0] AUD_IF_BYTE12[7:0] AUD_IF_BYTE13[7:0] AUD_IF_BYTE14[7:0] AUD_IF_BYTE15[7:0] AUD_IF_BYTE16[7:0] AUD_IF_BYTE17[7:0] AUD_IF_BYTE18[7:0] AUD_IF_BYTE19[7:0] AUD_IF_BYTE20[7:0] AUD_IF_BYTE21[7:0] AUD_IF_BYTE22[7:0] AUD_IF_BYTE23[7:0] AUD_IF_BYTE24[7:0] Default value
Product data sheet 67 of 119
TDA9983B_1
NXP Semiconductors
AUD_IF_BYTE6 AUD_IF_BYTE7 AUD_IF_BYTE8 AUD_IF_BYTE9 AUD_IF_BYTE10 AUD_IF_BYTE11 AUD_IF_BYTE12 AUD_IF_BYTE13 AUD_IF_BYTE14 AUD_IF_BYTE15 AUD_IF_BYTE16 AUD_IF_BYTE17 AUD_IF_BYTE18 AUD_IF_BYTE19 AUD_IF_BYTE20 AUD_IF_BYTE21 AUD_IF_BYTE22 AUD_IF_BYTE23 AUD_IF_BYTE24
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 83. Register AUD_IF_BYTE25 AUD_IF_BYTE26 AUD_IF_BYTE27 Not used MPS_IF_TYPE MPS_IF_VERSION MPS_IF_LENGTH MPS_IF_CHECKSUM MPS_IF_BYTE1 MPS_IF_BYTE2 MPS_IF_BYTE3 MPS_IF_BYTE4
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 10h[1] ...continued Sub addr 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h A7h A8h A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh R/W 7 (MSB) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W reserved x x x 6 5 4 Bit 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0000 0000 0000 1000 0101 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 MPS_IF_MF[1:0] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 AUD_IF_BYTE25[7:0] AUD_IF_BYTE26[7:0] AUD_IF_BYTE27[7:0] MPS_IF_TYPE[7:0] MPS_IF_VERSION[7:0] MPS_IF_LENGTH[4:0] MPS_IF_CHECKSUM[7:0] MPS_IF_MB0[7:0] MPS_IF_MB1[7:0] MPS_IF_MB2[7:0] MPS_IF_MB3[7:0] MPS_IF_ FR0 reserved Default value
Product data sheet 68 of 119
TDA9983B_1
NXP Semiconductors
MPS_IF_BYTE5 MPS_IF_BYTE6 MPS_IF_BYTE7 MPS_IF_BYTE8 MPS_IF_BYTE9 MPS_IF_BYTE10 MPS_IF_BYTE11 MPS_IF_BYTE12 MPS_IF_BYTE13 MPS_IF_BYTE14 MPS_IF_BYTE15 MPS_IF_BYTE16 MPS_IF_BYTE17 MPS_IF_BYTE18 MPS_IF_BYTE19 MPS_IF_BYTE20 MPS_IF_BYTE21 MPS_IF_BYTE22 MPS_IF_BYTE23
MPS_IF_BYTE6[7:0] MPS_IF_BYTE7[7:0] MPS_IF_BYTE8[7:0] MPS_IF_BYTE9[7:0] MPS_IF_BYTE10[7:0] MPS_IF_BYTE11[7:0] MPS_IF_BYTE12[7:0] MPS_IF_BYTE13[7:0] MPS_IF_BYTE14[7:0] MPS_IF_BYTE15[7:0] MPS_IF_BYTE16[7:0] MPS_IF_BYTE17[7:0] MPS_IF_BYTE18[7:0] MPS_IF_BYTE19[7:0] MPS_IF_BYTE20[7:0] MPS_IF_BYTE21[7:0] MPS_IF_BYTE22[7:0] MPS_IF_BYTE23[7:0]
150 MHz pixel rate HDMI transmitter
TDA9983B
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Table 83. Register MPS_IF_BYTE24 MPS_IF_BYTE25 MPS_IF_BYTE26 MPS_IF_BYTE27 Not used : Not used CURPAGE_ADR
[1]
I2C-bus registers of memory page 10h[1] ...continued Sub addr BBh BCh BDh BEh BFh : FEh FFh R/W 7 (MSB) R/W R/W R/W R/W : W 6 5 4 Bit 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000 MPS_IF_BYTE24[7:0] MPS_IF_BYTE25[7:0] MPS_IF_BYTE26[7:0] MPS_IF_BYTE27[7:0] : CURPAGE_ADR[7:0] Default value
Product data sheet Rev. 01 -- 20 May 2008 69 of 119
TDA9983B_1 (c) NXP B.V. 2008. All rights reserved.
NXP Semiconductors
R: reading register W: writing register x: bit must be set to default value for proper operation -: not used
150 MHz pixel rate HDMI transmitter
TDA9983B
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.6.1 Vendor-specific InfoFrame registers
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes.
Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description Legend: * = default value Address Register 20h VSP_IF_TYPE Bit Symbol Access Value Description R/W 81h* vendor-specific InfoFrame packet type: gives the packet type of the vendor-specific InfoFrame packet (80h + InfoFrame type code as per EIA/CEA-861B) vendor-specific InfoFrame version: gives the version number of the vendor-specific InfoFrame reserved (shall be 000) 7 to 0 VSP_IF_TYPE[7:0]
21h
VSP_IF_VERSION
7 to 0 VSP_IF_ VERSION[7:0] 7 to 5 x 4 to 0 VSP_IF_ LENGTH[4:0]
R/W
00h*
22h
VSP_IF_LENGTH
R/W R/W
000*
0 vendor-specific InfoFrame length: 0000* gives the number of data bytes for the vendor-specific InfoFrame; this length does not include the checksum 00h* vendor-specific InfoFrame checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the vendor-specific InfoFrame packet contents (determined by InfoFrame length) plus the checksum itself equals 0 vendor-specific InfoFrame IEEE: 24-bit IEEE registration identifier
23h
VSP_IF_ CHECKSUM
7 to 0 VSP_IF_ CHECKSUM[7:0]
R/W
24h 25h 26h
VSP_IF_IEEE_LSB VSP_IF_IEEE_ISB
7 to 0 VSP_IF_IEEE[7:0] 7 to 0 VSP_IF_IEEE[15:8]
R/W R/W R/W
00h* 00h* 00h*
VSP_IF_IEEE_MSB 7 to 0 VSP_IF_IEEE[23:16]
vendor-specific InfoFrame payload byte x: x = 4 to 27 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h
TDA9983B_1
VSP_IF_BYTE4 VSP_IF_BYTE5 VSP_IF_BYTE6 VSP_IF_BYTE7 VSP_IF_BYTE8 VSP_IF_BYTE9 VSP_IF_BYTE10 VSP_IF_BYTE11 VSP_IF_BYTE12 VSP_IF_BYTE13 VSP_IF_BYTE14 VSP_IF_BYTE15 VSP_IF_BYTE16 VSP_IF_BYTE17 VSP_IF_BYTE18 VSP_IF_BYTE19
7 to 0 VSP_IF_PB4[7:0] 7 to 0 VSP_IF_PB5[7:0] 7 to 0 VSP_IF_PB6[7:0] 7 to 0 VSP_IF_PB7[7:0] 7 to 0 VSP_IF_PB8[7:0] 7 to 0 VSP_IF_PB9[7:0] 7 to 0 VSP_IF_PB10[7:0] 7 to 0 VSP_IF_PB11[7:0] 7 to 0 VSP_IF_PB12[7:0] 7 to 0 VSP_IF_PB13[7:0] 7 to 0 VSP_IF_PB14[7:0] 7 to 0 VSP_IF_PB15[7:0] 7 to 0 VSP_IF_PB16[7:0] 7 to 0 VSP_IF_PB17[7:0] 7 to 0 VSP_IF_PB18[7:0] 7 to 0 VSP_IF_PB19[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h*
byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 byte 10 byte 11 byte 12 byte 13 byte 14 byte 15 byte 16 byte 17 byte 18 byte 19
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
70 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 84. VSP_IF_xx registers (address 20h to 3Eh) bit description ...continued Legend: * = default value Address Register 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh VSP_IF_BYTE20 VSP_IF_BYTE21 VSP_IF_BYTE22 VSP_IF_BYTE23 VSP_IF_BYTE24 VSP_IF_BYTE25 VSP_IF_BYTE26 VSP_IF_BYTE27 Bit Symbol Access Value Description R/W R/W R/W R/W R/W R/W R/W R/W 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* byte 20 byte 21 byte 22 byte 23 byte 24 byte 25 byte 26 byte 27 7 to 0 VSP_IF_PB20[7:0] 7 to 0 VSP_IF_PB21[7:0] 7 to 0 VSP_IF_PB22[7:0] 7 to 0 VSP_IF_PB23[7:0] 7 to 0 VSP_IF_PB24[7:0] 7 to 0 VSP_IF_PB25[7:0] 7 to 0 VSP_IF_PB26[7:0] 7 to 0 VSP_IF_PB27[7:0]
9.6.2 Auxiliary video information InfoFrame registers
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes.
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description Legend: * = default value Address Register 40h AVI_IF_TYPE Bit Symbol Access Value Description R/W 82h* auxiliary video information InfoFrame packet type: gives the packet type of the auxiliary video information InfoFrame packet (80h + InfoFrame type code as per EIA/CEA-861B) auxiliary video information InfoFrame version: gives the version number of the auxiliary video information InfoFrame reserved (shall be 000) 7 to 0 AVI_IF_TYPE[7:0]
41h
AVI_IF_VERSION
7 to 0 AVI_IF_VERSION[7:0]
R/W
00h*
42h
AVI_IF_LENGTH
7 to 5 x 4 to 0 AVI_IF_LENGTH[4:0]
R/W R/W
000*
0 auxiliary video information InfoFrame 0000* length: gives the number of data bytes for the auxiliary video information InfoFrame; this length does not include the checksum 00h* auxiliary video information InfoFrame checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the auxiliary video information InfoFrame packet contents (determined by InfoFrame length) plus the checksum itself equals 0
43h
AVI_IF_ CHECKSUM
7 to 0 AVI_IF_ CHECKSUM[7:0]
R/W
TDA9983B_1
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Product data sheet
Rev. 01 -- 20 May 2008
71 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description ...continued Legend: * = default value Address Register 44h AVI_IF_BYTE1 Bit 7 Symbol reserved Access Value Description R/W R/W 00* 01 10 11 4 AVI_IF_A R/W 0* 1 3 to 2 AVI_IF_B[1:0] R/W 00* 01 10 11 1 to 0 AVI_IF_S[1:0] R/W 00* 01 10 11 45h AVI_IF_BYTE2 7 to 6 AVI_IF_C[1:0] R/W 00* 01 10 11 5 to 4 AVI_IF_M[1:0] R/W 00* 01 10 11 3 to 0 AVI_IF_R[3:0] R/W 1000 1001 1010 1011 other
TDA9983B_1
0*
reserved (shall be zero) auxiliary video information InfoFrame Y: RGB or YCBCR indicator RGB YCBCR 4 : 2 : 2 YCBCR 4 : 4 : 4 future auxiliary video information InfoFrame A: active format information present no data active format information valid auxiliary video information InfoFrame bar: bar information bar data not valid vertical bar info valid horizontal bar info valid vertical and horizontal bar info valid auxiliary video information InfoFrame scan: scan information no data overscanned (television) underscanned (computer) future auxiliary video information InfoFrame colorimetry: colorimetry no data ITU601 ITU709 future auxiliary video information InfoFrame M: picture aspect ratio no data 4:3 16 : 9 future auxiliary video information InfoFrame ratio: active format aspect ratio same as picture aspect ratio 4 : 3 (center) 16 : 9 (center) 14 : 9 (center) per DVB AFD active_format field
(c) NXP B.V. 2008. All rights reserved.
6 to 5 AVI_IF_Y[1:0]
Product data sheet
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 85. AVI_IF_xx registers (address 40h to 5Eh) bit description ...continued Legend: * = default value Address Register 46h AVI_IF_BYTE3 Bit Symbol Access Value Description R/W R/W 00* 01 10 11 47h AVI_IF_BYTE4 7 reserved R/W R/W 0* 0000 00* reserved (shall be zero) auxiliary video information InfoFrame scaling: non-uniform picture scaling no known non-uniform scaling picture has been scaled horizontally picture has been scaled vertically picture has been scaled horizontally and vertically reserved (shall be zero) 7 to 2 reserved 1 to 0 AVI_IF_SC[1:0]
6 to 0 AVI_IF_VIC[6:0]
000 auxiliary video information InfoFrame 0000* video identification code: video identification code 0000* reserved (shall be zero) 0000* auxiliary video information InfoFrame pixel repetition: pixel repetition 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* auxiliary video information InfoFrame reserved byte x: x = 14 to 27 pixel number of start of right bar pixel number of end of left bar line number of start of bottom bar line number of end of top bar
48h
AVI_IF_BYTE5
7 to 4 reserved 3 to 0 AVI_IF_PR[3:0]
R/W R/W R/W R/W R/W R/W R/W R/W
49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h
AVI_IF_BYTE6 AVI_IF_BYTE7 AVI_IF_BYTE8 AVI_IF_BYTE9 AVI_IF_BYTE10 AVI_IF_BYTE11 AVI_IF_BYTE12 AVI_IF_BYTE13
7 to 0 LINE_E_TP_BAR[7:0] 7 to 0 LINE_S_BT_BAR[7:0] 7 to 0 PIX_E_LF_BAR[7:0] 7 to 0 PIX_E_LF_BAR[15:8] 7 to 0 PIX_S_RG_BAR[7:0] 7 to 0 PIX_S_RG_BAR[15:8]
7 to 0 LINE_E_TP_BAR[15:8] R/W 7 to 0 LINE_S_BT_BAR[15:8] R/W
51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch 5Dh 5Eh
AVI_IF_BYTE14 AVI_IF_BYTE15 AVI_IF_BYTE16 AVI_IF_BYTE17 AVI_IF_BYTE18 AVI_IF_BYTE19 AVI_IF_BYTE20 AVI_IF_BYTE21 AVI_IF_BYTE22 AVI_IF_BYTE23 AVI_IF_BYTE24 AVI_IF_BYTE25 AVI_IF_BYTE26 AVI_IF_BYTE27
7 to 0 AVI_IF_RB14[7:0] 7 to 0 AVI_IF_RB15[7:0] 7 to 0 AVI_IF_RB16[7:0] 7 to 0 AVI_IF_RB17[7:0] 7 to 0 AVI_IF_RB18[7:0] 7 to 0 AVI_IF_RB19[7:0] 7 to 0 AVI_IF_RB20[7:0] 7 to 0 AVI_IF_RB21[7:0] 7 to 0 AVI_IF_RB22[7:0] 7 to 0 AVI_IF_RB23[7:0] 7 to 0 AVI_IF_RB24[7:0] 7 to 0 AVI_IF_RB25[7:0] 7 to 0 AVI_IF_RB26[7:0] 7 to 0 AVI_IF_RB27[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h*
byte 14; reserved (shall be zero) byte 15; reserved (shall be zero) byte 16; reserved (shall be zero) byte 17; reserved (shall be zero) byte 18; reserved (shall be zero) byte 19; reserved (shall be zero) byte 20; reserved (shall be zero) byte 21; reserved (shall be zero) byte 22; reserved (shall be zero) byte 23; reserved (shall be zero) byte 24; reserved (shall be zero) byte 25; reserved (shall be zero) byte 26; reserved (shall be zero) byte 27; reserved (shall be zero)
TDA9983B_1
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Product data sheet
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.6.3 Source product description InfoFrame registers
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes.
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description Legend: * = default value Address Register 60h SPD_IF_TYPE Bit Symbol Access Value R/W 83h* Description source product description InfoFrame packet type: gives the packet type of the source product description InfoFrame packet (80h + InfoFrame type code as per EIA/CEA-861B) source product description InfoFrame version: gives the version number of the source product description InfoFrame reserved (shall be 000) source product description InfoFrame length: gives the number of data bytes for the source product description InfoFrame; this length does not include the checksum source product description InfoFrame checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the source product description InfoFrame packet contents (determined by InfoFrame length) plus the checksum itself equals 0 source product description InfoFrame vendor name: 7-bit ASCII code 64h 65h 66h 67h 68h 69h 6Ah SPD_IF_BYTE1 SPD_IF_BYTE2 SPD_IF_BYTE3 SPD_IF_BYTE4 SPD_IF_BYTE5 SPD_IF_BYTE6 SPD_IF_BYTE7 7 7 7 7 7 7 7 x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* reserved (shall be zero) character 1 reserved (shall be zero) character 2 reserved (shall be zero) character 3 reserved (shall be zero) character 4 reserved (shall be zero) character 5 reserved (shall be zero) character 6 reserved (shall be zero) character 7
(c) NXP B.V. 2008. All rights reserved.
7 to 0 SPD_IF_TYPE[7:0]
61h
SPD_IF_VERSION
7 to 0 SPD_IF_ VERSION[7:0]
R/W
00h*
62h
SPD_IF_LENGTH
7 to 5 x
R/W
000* 0 0000*
4 to 0 SPD_IF_LENGTH[4:0] R/W
63h
SPD_IF_CHECKSUM 7 to 0 SPD_IF_ CHECKSUM[7:0]
R/W
00h*
6 to 0 SPD_IF_VN1[6:0] 6 to 0 SPD_IF_VN2[6:0] 6 to 0 SPD_IF_VN3[6:0] 6 to 0 SPD_IF_VN4[6:0] 6 to 0 SPD_IF_VN5[6:0] 6 to 0 SPD_IF_VN6[6:0] 6 to 0 SPD_IF_VN7[6:0]
TDA9983B_1
Product data sheet
Rev. 01 -- 20 May 2008
74 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 6Bh SPD_IF_BYTE8 Bit 7 Symbol x Access Value R/W R/W 0* 000 0000* Description reserved (shall be zero) character 8 source product description InfoFrame product description: 7-bit ASCII code 6Ch 6Dh 6Eh 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h 7Ah 7Bh SPD_IF_BYTE9 SPD_IF_BYTE10 SPD_IF_BYTE11 SPD_IF_BYTE12 SPD_IF_BYTE13 SPD_IF_BYTE14 SPD_IF_BYTE15 SPD_IF_BYTE16 SPD_IF_BYTE17 SPD_IF_BYTE18 SPD_IF_BYTE19 SPD_IF_BYTE20 SPD_IF_BYTE21 SPD_IF_BYTE22 SPD_IF_BYTE23 SPD_IF_BYTE24 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 x x x x x x x x x x x x x x x x R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* 0* 000 0000* reserved (shall be zero) character 1 reserved (shall be zero) character 2 reserved (shall be zero) character 3 reserved (shall be zero) character 4 reserved (shall be zero) character 5 reserved (shall be zero) character 6 reserved (shall be zero) character 7 reserved (shall be zero) character 8 reserved (shall be zero) character 9 reserved (shall be zero) character 10 reserved (shall be zero) character 11 reserved (shall be zero) character 12 reserved (shall be zero) character 13 reserved (shall be zero) character 14 reserved (shall be zero) character 15 reserved (shall be zero) character 16 6 to 0 SPD_IF_PD1[6:0] 6 to 0 SPD_IF_PD2[6:0] 6 to 0 SPD_IF_PD3[6:0] 6 to 0 SPD_IF_PD4[6:0] 6 to 0 SPD_IF_PD5[6:0] 6 to 0 SPD_IF_PD6[6:0] 6 to 0 SPD_IF_PD7[6:0] 6 to 0 SPD_IF_PD8[6:0] 6 to 0 SPD_IF_PD9[6:0] 6 to 0 SPD_IF_PD10[6:0] 6 to 0 SPD_IF_PD11[6:0] 6 to 0 SPD_IF_PD12[6:0] 6 to 0 SPD_IF_PD13[6:0] 6 to 0 SPD_IF_PD14[6:0] 6 to 0 SPD_IF_PD15[6:0] 6 to 0 SPD_IF_PD16[6:0]
6 to 0 SPD_IF_VN8[6:0]
TDA9983B_1
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Product data sheet
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 86. SPD_IF_xx registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 7Ch SPD_IF_BYTE25 Bit Symbol Access Value R/W Description source product description InfoFrame source device information: source device information 00h* 01h 02h 03h 04h 05h 06h 07h 08h 09h unknown digital STB DVD D-VHS HDD video DVC DSC video CD game PC general source product description InfoFrame data byte 7Dh 7Eh SPD_IF_BYTE26 SPD_IF_BYTE27 7 to 0 SPD_IF_BYTE26[7:0] 7 to 0 SPD_IF_BYTE27[7:0] R/W R/W 00h* 00h* data byte 26 data byte 27 7 to 0 SPD_IF_SDI[7:0]
9.6.4 Audio InfoFrame registers
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes.
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description Legend: * = default value Address Register 80h AUD_IF_TYPE Bit Symbol Access Value R/W 84h* Description audio InfoFrame packet type: gives the packet type of the audio InfoFrame packet (80h + InfoFrame type code as per EIA/CEA-861B) audio InfoFrame version: gives the version number of the audio InfoFrame reserved (shall be zero) audio InfoFrame length: gives the number of data bytes for the audio InfoFrame; this length does not include the checksum audio InfoFrame checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the audio InfoFrame packet contents (determined by InfoFrame length) plus the checksum itself equals 0
(c) NXP B.V. 2008. All rights reserved.
7 to 0 AUD_IF_TYPE[7:0]
81h
AUD_IF_VERSION
7 to 0 AUD_IF_ VERSION[7:0] 7 to 5 x
R/W
00h*
82h
AUD_IF_LENGTH
R/W
000* 0 0000*
4 to 0 AUD_IF_LENGTH[4:0] R/W
83h
AUD_IF_CHECKSUM 7 to 0 AUD_IF_ CHECKSUM[7:0]
R/W
00h*
TDA9983B_1
Product data sheet
Rev. 01 -- 20 May 2008
76 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description ...continued Legend: * = default value Address Register 84h AUD_IF_BYTE1 Bit Symbol Access Value R/W 0000* 0001 0010 0011 0100 0101 0110 0111 1000 other 3 reserved R/W R/W 000* 001 010 011 100 101 110 111 85h AUD_IF_BYTE2 7 to 5 reserved 4 to 2 AUD_IF_SF[2:0] R/W R/W 000* 001 010 011 100 101 110 111 1 to 0 AUD_IF_SS[1:0] R/W 00* 01 10 11 000* 0* 2 to 0 AUD_IF_CC[2:0] Description audio InfoFrame coding type: audio coding type refer to stream header IEC 60958 PCM AC-3 MPEG1 MP3 MPEG2 AAC DTS ATRAC undefined reserved bit audio InfoFrame channel count: audio channel count refer to stream header 2 channels 3 channels 4 channels 5 channels 6 channels 7 channels 8 channels reserved (shall be zero) audio InfoFrame sampling frequency: sampling frequency refer to stream header 32 kHz 44.1 kHz (CD) 48 kHz 88.2 kHz 96 kHz 176.4 kHz 192 kHz audio InfoFrame sample size: sample size refer to stream header 16 bits 20 bits 24 bits 7 to 4 AUD_IF_CT[3:0]
TDA9983B_1
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Product data sheet
Rev. 01 -- 20 May 2008
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description ...continued Legend: * = default value Address Register 86h AUD_IF_BYTE3 Bit Symbol Access Value R/W 00h* Description audio InfoFrame data byte 3: value x 8 kHz = maximum bit rate of audio stream (compressed audio format) audio InfoFrame channel allocation: channel allocation (LPCM) audio InfoFrame down-mix inhibit flag: down-mix inhibit flag 0* 1 6 to 3 AUD_IF_LSV[3:0] R/W 0000* 0001 0010 0011 1000 : 1111 2 to 0 reserved R/W 000* permitted or no information about any assertion of this prohibited audio InfoFrame level shift value: level shift value 0 dB 1 dB 2 dB 3 dB 4 dB : 15 dB reserved (shall be 000h) audio InfoFrame data byte x: x = 6 to 27 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah AUD_IF_BYTE6 AUD_IF_BYTE7 AUD_IF_BYTE8 AUD_IF_BYTE9 AUD_IF_BYTE10 AUD_IF_BYTE11 AUD_IF_BYTE12 AUD_IF_BYTE13 AUD_IF_BYTE14 AUD_IF_BYTE15 AUD_IF_BYTE16 AUD_IF_BYTE17 AUD_IF_BYTE18 AUD_IF_BYTE19 AUD_IF_BYTE20 AUD_IF_BYTE21 AUD_IF_BYTE22 AUD_IF_BYTE23 7 to 0 AUD_IF_BYTE6[7:0] 6 to 0 AUD_IF_BYTE7[7:0] 6 to 0 AUD_IF_BYTE8[7:0] 6 to 0 AUD_IF_BYTE9[7:0] 7 to 0 AUD_IF_BYTE10[7:0] 7 to 0 AUD_IF_BYTE11[7:0] 7 to 0 AUD_IF_BYTE12[7:0] 7 to 0 AUD_IF_BYTE13[7:0] 7 to 0 AUD_IF_BYTE14[7:0] 7 to 0 AUD_IF_BYTE15[7:0] 7 to 0 AUD_IF_BYTE16[7:0] 7 to 0 AUD_IF_BYTE17[7:0] 7 to 0 AUD_IF_BYTE18[7:0] 7 to 0 AUD_IF_BYTE19[7:0] 7 to 0 AUD_IF_BYTE20[7:0] 7 to 0 AUD_IF_BYTE21[7:0] 7 to 0 AUD_IF_BYTE22[7:0] 7 to 0 AUD_IF_BYTE23[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* byte 6: reserved (shall be zero) byte 7: reserved (shall be zero) byte 8: reserved (shall be zero) byte 9: reserved (shall be zero) byte 10: reserved (shall be zero) byte 11: reserved (shall be zero) byte 12: reserved (shall be zero) byte 13: reserved (shall be zero) byte 14: reserved (shall be zero) byte 15: reserved (shall be zero) byte 16: reserved (shall be zero) byte 17: reserved (shall be zero) byte 18: reserved (shall be zero) byte 19: reserved (shall be zero) byte 20: reserved (shall be zero) byte 21: reserved (shall be zero) byte 22: reserved (shall be zero) byte 23: reserved (shall be zero) 7 to 0 AUD_IF_BYTE3[7:0]
87h
AUD_IF_BYTE4
7 to 0 AUD_IF_CA[7:0]
R/W
00h*
88h
AUD_IF_BYTE5
7
AUD_IF_DM_INH
R/W
TDA9983B_1
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Product data sheet
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 87. AUD_IF_xx registers (address 80h to 9Eh) bit description ...continued Legend: * = default value Address Register 9Bh 9Ch 9Dh 9Eh AUD_IF_BYTE24 AUD_IF_BYTE25 AUD_IF_BYTE26 AUD_IF_BYTE27 Bit Symbol Access Value R/W R/W R/W R/W 00h* 00h* 00h* 00h* Description byte 24: reserved (shall be zero) byte 25: reserved (shall be zero) byte 26: reserved (shall be zero) byte 27: reserved (shall be zero) 7 to 0 AUD_IF_BYTE24[7:0] 7 to 0 AUD_IF_BYTE25[7:0] 7 to 0 AUD_IF_BYTE26[7:0] 7 to 0 AUD_IF_BYTE27[7:0]
9.6.5 MPEG source InfoFrame registers
Below is an example of use. Please refer to EIA/CEA-861B specification and HDMI 1.2a specification for the correct definition of data bytes.
Table 88. MPS_IF_xx registers (address A0h to BEh) bit description Legend: * = default value Address Register A0h MPS_IF_TYPE Bit Symbol Access Value R/W 85h* Description MPEG source InfoFrame packet type: gives the packet type of the MPEG source InfoFrame packet (80h + InfoFrame type code as per EIA/CEA-861B) MPEG source InfoFrame version: gives the version number of the MPEG source InfoFrame reserved (shall be zero) MPEG source InfoFrame length: gives the number of data bytes for the MPEG source InfoFrame; this length does not include the checksum MPEG source InfoFrame checksum: shall be calculated such that a byte-wide sum of all three bytes of the packet header and all valid bytes of the MPEG source InfoFrame packet contents (determined by InfoFrame length) plus the checksum itself equals 0 MPEG source InfoFrame MPEG bit rate (Hz) A4h A5h A6h A7h MPS_IF_BYTE1 MPS_IF_BYTE2 MPS_IF_BYTE3 MPS_IF_BYTE4 7 to 0 MPS_IF_MB0[7:0] 7 to 0 MPS_IF_MB1[7:0] 7 to 0 MPS_IF_MB2[7:0] 7 to 0 MPS_IF_MB3[7:0] R/W R/W R/W R/W 00h* 00h* 00h* 00h* MB#0 (lower byte) MB#1 (medium byte) MB#2 (medium byte) MB#3 (upper byte) 7 to 0 MPS_IF_TYPE[7:0]
A1h
MPS_IF_VERSION
7 to 0 MPS_IF_VERSION[7:0]
R/W
00h*
A2h
MPS_IF_LENGTH
7 to 5 x 4 to 0 MPS_IF_LENGTH[4:0]
R/W R/W
000* 0 0000*
A3h
MPS_IF_ CHECKSUM
7 to 0 MPS_IF_ CHECKSUM[7:0]
R/W
00h*
TDA9983B_1
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Product data sheet
Rev. 01 -- 20 May 2008
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 88. MPS_IF_xx registers (address A0h to BEh) bit description ...continued Legend: * = default value Address Register A8h MPS_IF_BYTE5 Bit 4 Symbol MPS_IF_FR0 Access Value R/W R/W 0* 1 3 to 2 reserved 1 to 0 MPS_IF_MF[1:0] R/W R/W 00* 01 10 11 00* 000* Description reserved MPEG source InfoFrame field repeat 0: for 3 : 2 pull-down new field (picture) repeated field reserved MPEG source InfoFrame MPEG frame: MPEG frame unknown (no data) I picture B picture P picture MPEG source InfoFrame byte x: x = 6 to 27 A9h AAh ABh ACh ADh AEh AFh B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh MPS_IF_BYTE6 MPS_IF_BYTE7 MPS_IF_BYTE8 MPS_IF_BYTE9 MPS_IF_BYTE10 MPS_IF_BYTE11 MPS_IF_BYTE12 MPS_IF_BYTE13 MPS_IF_BYTE14 MPS_IF_BYTE15 MPS_IF_BYTE16 MPS_IF_BYTE17 MPS_IF_BYTE18 MPS_IF_BYTE19 MPS_IF_BYTE20 MPS_IF_BYTE21 MPS_IF_BYTE22 MPS_IF_BYTE23 MPS_IF_BYTE24 MPS_IF_BYTE25 MPS_IF_BYTE26 MPS_IF_BYTE27 7 to 0 MPS_IF_BYTE6[7:0] 6 to 0 MPS_IF_BYTE7[7:0] 6 to 0 MPS_IF_BYTE8[7:0] 6 to 0 MPS_IF_BYTE9[7:0] 7 to 0 MPS_IF_BYTE10[7:0] 7 to 0 MPS_IF_BYTE11[7:0] 7 to 0 MPS_IF_BYTE12[7:0] 7 to 0 MPS_IF_BYTE13[7:0] 7 to 0 MPS_IF_BYTE14[7:0] 7 to 0 MPS_IF_BYTE15[7:0] 7 to 0 MPS_IF_BYTE16[7:0] 7 to 0 MPS_IF_BYTE17[7:0] 7 to 0 MPS_IF_BYTE18[7:0] 7 to 0 MPS_IF_BYTE19[7:0] 7 to 0 MPS_IF_BYTE20[7:0] 7 to 0 MPS_IF_BYTE21[7:0] 7 to 0 MPS_IF_BYTE22[7:0] 7 to 0 MPS_IF_BYTE23[7:0] 7 to 0 MPS_IF_BYTE24[7:0] 7 to 0 MPS_IF_BYTE25[7:0] 7 to 0 MPS_IF_BYTE26[7:0] 7 to 0 MPS_IF_BYTE27[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h* 000 0000* 000 0000* 000 0000* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* byte 6: reserved (shall be zero) byte 7: reserved (shall be zero) byte 8: reserved (shall be zero) byte 9: reserved (shall be zero) byte 10: reserved (shall be zero) byte 11: reserved byte 12: reserved byte 13: reserved byte 14: reserved byte 15: reserved byte 16: reserved byte 17: reserved byte 18: reserved byte 19: reserved byte 20: reserved byte 21: reserved byte 22: reserved byte 23: reserved byte 24: reserved byte 25: reserved byte 26: reserved byte 27: reserved 7 to 5 reserved
TDA9983B_1
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Product data sheet
Rev. 01 -- 20 May 2008
80 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.6.6 Current page address register
Table 89. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol Access Value Description 00h* current page address: selects the current memory page CURPAGE_ADR[7:0] W
9.7 Audio settings and content info packets page register definitions
The current page address for the audio settings and content info packets page is 11h. The configuration of the registers for this page is given in Table 90.
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
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Product data sheet Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved. TDA9983B_1
NXP Semiconductors
Table 90. Register
I2C-bus registers of memory page 11h[1] Sub R/W addr 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W x x x x FORCE_ NULL x x x x x NULL x IF5 x x x x x x CTL_CODE[1:0] ISRC2 IF3 : CH_STAT_BYTE_0[7:0] CH_STAT_BYTE_1[7:0] CH_STAT_BYTE_3[7:0] CH_STAT_BYTE_4[7:0] CH_STAT_BYTE_2_AP0_L[7:0] CH_STAT_BYTE_2_AP0_R[7:0] CH_STAT_BYTE_2_AP1_L[7:0] CH_STAT_BYTE_2_AP1_R[7:0] CH_STAT_BYTE_2_AP2_L[7:0] CH_STAT_BYTE_2_AP2_R[7:0] CH_STAT_BYTE_2_AP3_L[7:0] ISRC1 IF2 GC IF1 x x x x x N[7:0] N[15:8] N[19:16] SET_ MUTE K_SEL[2:0] DC_CTL[1:0] ACR x CLR_MUTE Bit 7 (MSB) x x x x 6 x x x 5 x x x x x x x CTS[7:0] CTS[15:8] CTS[19:16] 4 x 3 x 2 LAYOUT CA_I2S[4:0] x x x x x x 1 SWAP 0 (LSB) RST_FIFO 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 0111 1000 0110 1001 0000 0000 0000 0000 0110 0000 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RST_CTS ACR_MAN Default value
AIP_CNTRL_0 CA_I2S For test For test LATENCY_RD ACR_CTS_0 ACR_CTS_1 ACR_CTS_2 ACR_N_0 ACR_N_1 ACR_N_2 GC_AVMUTE CTS_N ENC_CNTRL DIP_FLAGS DIP_IF_FLAGS Not used : Not used CH_STAT_B_0 CH_STAT_B_1 CH_STAT_B_3 CH_STAT_B_4 CH_STAT_B_2_AP0_L CH_STAT_B_2_AP0_R CH_STAT_B_2_AP1_L CH_STAT_B_2_AP1_R CH_STAT_B_2_AP2_L CH_STAT_B_2_AP2_R CH_STAT_B_2_AP3_L
LATENCY_RD[7:0]
0Ah R/W 0Bh R/W 0Ch R/W 0Dh R/W 0Eh R/W 0Fh 10h : 13h 14h 15h 16h 17h 18h 19h R/W : R/W R/W R/W R/W R/W R/W
M_SEL[1:0] x x ACP IF4
150 MHz pixel rate HDMI transmitter
TDA9983B
1Ah R/W 1Bh R/W 1Ch R/W 1Dh R/W 1Eh R/W
82 of 119
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Table 90. Register CH_STAT_B_2_AP3_R ISRC1_PACKET_TYPE ISRC1_CTRL ISRC1_RSVD UPC_EAN_ISRC_0 UPC_EAN_ISRC_1 UPC_EAN_ISRC_2 UPC_EAN_ISRC_3 UPC_EAN_ISRC_4 UPC_EAN_ISRC_5 UPC_EAN_ISRC_6
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 11h[1] ...continued Sub R/W addr 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ISRC_ CONT ISRC_ VALID Bit 7 (MSB) 6 5 4 3 2 1 0 (LSB) 0000 0000 0000 0101 ISRC_STATUS[2:0] 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CH_STAT_BYTE_2_AP3_R[7:0] ISRC1_PACKET_TYPE[7:0] ISRC1_RSVD[5:3] ISRC1_RSVD[7:0] UPC_EAN_ISRC_0[7:0] UPC_EAN_ISRC_1[7:0] UPC_EAN_ISRC_2[7:0] UPC_EAN_ISRC_3[7:0] UPC_EAN_ISRC_4[7:0] UPC_EAN_ISRC_5[7:0] UPC_EAN_ISRC_6[7:0] UPC_EAN_ISRC_7[7:0] UPC_EAN_ISRC_8[7:0] UPC_EAN_ISRC_9[7:0] UPC_EAN_ISRC_10[7:0] UPC_EAN_ISRC_11[7:0] UPC_EAN_ISRC_12[7:0] UPC_EAN_ISRC_13[7:0] UPC_EAN_ISRC_14[7:0] UPC_EAN_ISRC_15[7:0] ISRC1_PB_BYTE_16[7:0] ISRC1_PB_BYTE_17[7:0] ISRC1_PB_BYTE_18[7:0] ISRC1_PB_BYTE_19[7:0] ISRC1_PB_BYTE_20[7:0] ISRC1_PB_BYTE_21[7:0] ISRC1_PB_BYTE_22[7:0] ISRC1_PB_BYTE_23[7:0] ISRC1_PB_BYTE_24[7:0] ISRC1_PB_BYTE_25[7:0] ISRC1_PB_BYTE_26[7:0] Default value
Product data sheet 83 of 119
TDA9983B_1
NXP Semiconductors
UPC_EAN_ISRC_7 UPC_EAN_ISRC_8 UPC_EAN_ISRC_9 UPC_EAN_ISRC_10 UPC_EAN_ISRC_11 UPC_EAN_ISRC_12 UPC_EAN_ISRC_13 UPC_EAN_ISRC_14 UPC_EAN_ISRC_15 ISRC1_PB16 ISRC1_PB17 ISRC1_PB18 ISRC1_PB19 ISRC1_PB20 ISRC1_PB21 ISRC1_PB22 ISRC1_PB23 ISRC1_PB24 ISRC1_PB25 ISRC1_PB26
2Ah R/W 2Bh R/W 2Ch R/W 2Dh R/W 2Eh R/W 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
150 MHz pixel rate HDMI transmitter
TDA9983B
3Ah R/W 3Bh R/W 3Ch R/W 3Dh R/W
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Table 90. Register ISRC1_PB27 Not used ISRC2_PACKET_TYPE ISRC2_RSVD1 ISRC2_RSVD2 UPC_EAN_ISRC_16 UPC_EAN_ISRC_17 UPC_EAN_ISRC_18 UPC_EAN_ISRC_19 UPC_EAN_ISRC_20 UPC_EAN_ISRC_21 UPC_EAN_ISRC_22
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 11h[1] ...continued Sub R/W addr 3Eh R/W 3Fh 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 (MSB) 6 5 4 ISRC2_PACKET_TYPE[7:0] ISRC2_RSVD1[7:0] ISRC2_RSVD2[7:0] UPC_EAN_ISRC_16[7:0] UPC_EAN_ISRC_17[7:0] UPC_EAN_ISRC_18[7:0] UPC_EAN_ISRC_19[7:0] UPC_EAN_ISRC_20[7:0] UPC_EAN_ISRC_21[7:0] UPC_EAN_ISRC_22[7:0] UPC_EAN_ISRC_23[7:0] UPC_EAN_ISRC_24[7:0] UPC_EAN_ISRC_25[7:0] UPC_EAN_ISRC_26[7:0] UPC_EAN_ISRC_27[7:0] UPC_EAN_ISRC_28[7:0] UPC_EAN_ISRC_29[7:0] UPC_EAN_ISRC_30[7:0] UPC_EAN_ISRC_31[7:0] ISRC2_PB_BYTE_16[7:0] ISRC2_PB_BYTE_17[7:0] ISRC2_PB_BYTE_18[7:0] ISRC2_PB_BYTE_19[7:0] ISRC2_PB_BYTE_20[7:0] ISRC2_PB_BYTE_21[7:0] ISRC2_PB_BYTE_22[7:0] ISRC2_PB_BYTE_23[7:0] ISRC2_PB_BYTE_24[7:0] ISRC2_PB_BYTE_25[7:0] ISRC2_PB_BYTE_26[7:0] 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ISRC1_PB_BYTE_27[7:0] Default value
Product data sheet 84 of 119
TDA9983B_1
NXP Semiconductors
UPC_EAN_ISRC_23 UPC_EAN_ISRC_24 UPC_EAN_ISRC_25 UPC_EAN_ISRC_26 UPC_EAN_ISRC_27 UPC_EAN_ISRC_28 UPC_EAN_ISRC_29 UPC_EAN_ISRC_30 UPC_EAN_ISRC_31 ISRC2_PB16 ISRC2_PB17 ISRC2_PB18 ISRC2_PB19 ISRC2_PB20 ISRC2_PB21 ISRC2_PB22 ISRC2_PB23 ISRC2_PB24 ISRC2_PB25 ISRC2_PB26
4Ah R/W 4Bh R/W 4Ch R/W 4Dh R/W 4Eh R/W 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
150 MHz pixel rate HDMI transmitter
TDA9983B
5Ah R/W 5Bh R/W 5Ch R/W 5Dh R/W
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Table 90. Register ISRC2_PB27 Not used ACP_PACKET_TYPE ACP_TYPE ACP_RSVD ACP_PB0 ACP_PB1 ACP_PB2 ACP_PB3 ACP_PB4 ACP_PB5 ACP_PB6
Rev. 01 -- 20 May 2008
(c) NXP B.V. 2008. All rights reserved.
I2C-bus registers of memory page 11h[1] ...continued Sub R/W addr 5Eh R/W 5Fh 60h 61h 62h 63h 64h 65h 66h 67h 68h 69h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 (MSB) 6 5 4 ACP_PACKET_TYPE[7:0] ACP_TYPE[7:0] ACP_RSVD[7:0] ACP_PB_BYTE_0[7:0] ACP_PB_BYTE_1[7:0] ACP_PB_BYTE_2[7:0] ACP_PB_BYTE_3[7:0] ACP_PB_BYTE_4[7:0] ACP_PB_BYTE_5[7:0] ACP_PB_BYTE_6[7:0] ACP_PB_BYTE_7[7:0] ACP_PB_BYTE_8[7:0] ACP_PB_BYTE_9[7:0] ACP_PB_BYTE_10[7:0] ACP_PB_BYTE_11[7:0] ACP_PB_BYTE_12[7:0] ACP_PB_BYTE_13[7:0] ACP_PB_BYTE_14[7:0] ACP_PB_BYTE_15[7:0] ACP_PB_BYTE_16[7:0] ACP_PB_BYTE_17[7:0] ACP_PB_BYTE_18[7:0] ACP_PB_BYTE_19[7:0] ACP_PB_BYTE_20[7:0] ACP_PB_BYTE_21[7:0] ACP_PB_BYTE_22[7:0] ACP_PB_BYTE_23[7:0] ACP_PB_BYTE_24[7:0] ACP_PB_BYTE_25[7:0] ACP_PB_BYTE_26[7:0] 3 2 1 0 (LSB) 0000 0000 0000 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ISRC2_PB_BYTE_27[7:0] Default value
Product data sheet 85 of 119
TDA9983B_1
NXP Semiconductors
ACP_PB7 ACP_PB8 ACP_PB9 ACP_PB10 ACP_PB11 ACP_PB12 ACP_PB13 ACP_PB14 ACP_PB15 ACP_PB16 ACP_PB17 ACP_PB18 ACP_PB19 ACP_PB20 ACP_PB21 ACP_PB22 ACP_PB23 ACP_PB24 ACP_PB25 ACP_PB26
6Ah R/W 6Bh R/W 6Ch R/W 6Dh R/W 6Eh R/W 6Fh 70h 71h 72h 73h 74h 75h 76h 77h 78h 79h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
150 MHz pixel rate HDMI transmitter
TDA9983B
7Ah R/W 7Bh R/W 7Ch R/W 7Dh R/W
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Table 90. Register ACP_PB27 Not used : Not used CURPAGE_ADR
[1]
I2C-bus registers of memory page 11h[1] ...continued Sub R/W addr 7Eh R/W 7Fh : FEh FFh : W Bit 7 (MSB) 6 5 4 : CURPAGE_ADR[7:0] 3 2 1 0 (LSB) 0000 0000 0000 0000 : 0000 0000 0000 0000 ACP_PB_BYTE_27[7:0] Default value
Product data sheet Rev. 01 -- 20 May 2008 86 of 119
TDA9983B_1 (c) NXP B.V. 2008. All rights reserved.
NXP Semiconductors
R: reading register W: writing register x: bit must be set to default value for proper operation -: not used
150 MHz pixel rate HDMI transmitter
TDA9983B
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.7.1 Audio input processor control registers
Table 91. AIP_CNTRL_0 register (address 00h) bit description Legend: * = default value Bit 7 6 Symbol x RST_CTS Access Value R/W R/W 0* 1 5 ACR_MAN R/W 0* 1 4 to 3 2 x LAYOUT R/W R/W 0* 1 1 0 SWAP RST_FIFO R/W R/W 0* 1 0* 00* 0* Description undefined reset CTS no specific action reset CTS generation (soft reset) audio clock regeneration manual automatic audio clock regeneration time stamp generation manual audio clock regeneration time stamp generation undefined layout set layout 0 set layout 1 swap: for internal use reset FIFO no specific action reset audio FIFO
Table 92. CA_I2S register (address 01h) bit description Legend: * = default value Bit 7 to 5 4 to 0 Symbol x CA_I2S[4:0] Access Value R/W R/W 000* Description undefined
0 0000* channel allocation I2S-bus port: layout 1
Table 93. LATENCY_RD register (address 04h) bit description Legend: * = default value Bit 7 to 0 Symbol LATENCY_RD[7:0] Access Value R/W 04h* Description latency read: latency value in audio FIFO
Table 94. ACR_CTS_x registers (address 05h to 07h) bit description Legend: * = default value Address Register 07h 06h 05h ACR_CTS_2 ACR_CTS_1 ACR_CTS_0 Bit 7 to 4 3 to 0 7 to 0 7 to 0 Symbol x CTS[19:16] CTS[15:8] CTS[7:0] Access Value R/W R/W R/W R/W 0000* 0000* 69h* 78h* Description undefined CTS: audio clock recovery CTS value for manual CTS settings
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
87 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 95. ACR_N_x registers (address 08h to 0Ah) bit description Legend: * = default value Address Register 0Ah 09h 08h ACR_N_2 ACR_N_1 ACR_N_0 Bit Symbol Access Value R/W R/W R/W R/W 0000* 0000* 60h* 00h* Description undefined N: audio clock recovery N value for manual N-settings 7 to 4 x 3 to 0 N[19:16] 7 to 0 N[15:8] 7 to 0 N[7:0]
Table 96. GC_AVMUTE register (address 0Bh) bit description Legend: * = default value Bit 7 to 2 1 Symbol x SET_MUTE Access Value R/W R/W 0* 1 0 CLR_MUTE R/W 0* 1 Description set mute: GCP.SB0 (bit 0) no specific action set AVMUTE flag clear mute: GCP.SB0 (bit 4) no specific action clear AVMUTE flag 0000 00* undefined
Table 97. CTS_N register (address 0Ch) bit description Legend: * = default value Bit 7 to 6 5 to 4 Symbol x M_SEL[1:0] Access Value R/W R/W 00* 01 10 11 3 2 to 0 x K_SEL[2:0] R/W R/W 000* 001 010 011 1XX 0* 00* Description undefined M select: postdivider mts (measured time stamp) CTS = mts CTS = mts / 2 CTS = mts / 4 CTS = mts / 8 undefined K select: predivider (scales n) k=1 k=2 k=3 k=4 k=8
Table 98. ENC_CNTRL register (address 0Dh) bit description Legend: * = default value Bit 7 to 4 Symbol x Access Value R/W 0000* Description undefined
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
88 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 98. ENC_CNTRL register (address 0Dh) bit description ...continued Legend: * = default value Bit 3 to 2 Symbol CTL_CODE[1:0] Access Value R/W 00 01* 10 11 1 to 0 DC_CTL[1:0] R/W 00* 01 10 11 Description control code: force CTL[1:0] CTL[1:0] = 00 (DVI mode) CTL[1:0] = 01 (advised to use in case of HDMI mode) CTL[1:0] = 10 (only for debugging purposes) CTL[1:0] = 11 (only for debugging purposes) disparity counter control video guard band initializes disparity_cnt video_data_enable enables disparity_cnt free-running disparity_cnt undefined
Table 99. DIP_FLAGS register (address 0Eh) bit description Legend: * = default value Bit 7 Symbol FORCE_NULL Access Value R/W 0* 1 6 NULL R/W 0* 1 5 R/W 0* 1 4 ACP R/W Description force null no specific action insert null-packets continuously null no specific action insert one null-packet (this bit is reset by internal control) -: data packet header/contents as specified by registers 80h to 9Eh no specific action insert InfoFrame in first free slot after the keepout window audio content protection: data packet header/contents as specified by registers 60h to 7Eh (see Table 105) 0* 1 3 ISRC2 R/W no specific action insert 'acp' in first free slot after the keepout window international standard recording code 2: data packet header/contents as specified by registers 40h to 5Eh (see Table 104) 0* 1 no specific action insert 'isrc2' in first free slot after the keepout window
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
89 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 99. DIP_FLAGS register (address 0Eh) bit description ...continued Legend: * = default value Bit 2 Symbol ISRC1 Access Value R/W Description international standard recording code 1: data packet header/contents as specified by registers 20h to 3Eh (see Table 103) 0* 1 1 GC R/W 0* 1 0 ACR R/W 0* 1 no specific action insert 'isrc1' in first free slot after the keepout window general control no specific action insert general control packet (just after v-pulse) audio clock regeneration no specific action insert audio clock regeneration packets
Table 100. DIP_IF_FLAGS register (address 0Fh) bit description Legend: * = default value Bit 7 to 6 5 Symbol x IF5 Access Value R/W R/W 0* 1 4 IF4 R/W 0* 1 3 IF3 R/W 0* 1 2 IF2 R/W 0* 1 1 IF1 R/W 0* 1 0
TDA9983B_1
Description undefined if5: data packet header/contents as specified by registers A0h to BEh (page 10h) no specific action insert 'if5' in first free slot after the keepout window if4: data packet header/contents as specified by registers 80h to 9Eh (page 10h) no specific action insert 'if4' in first free slot after the keepout window if3: data packet header/contents as specified by registers 60h to 7Eh (page 10h) no specific action insert 'if3' in first free slot after the keepout window if2: data packet header/contents as specified by registers 40h to 5Eh (page 10h) no specific action insert 'if2' in first free slot after the keepout window if1: data packet header/contents as specified by registers 20h to 3Eh (page 10h) no specific action insert 'if1' in first free slot after the keepout window undefined
(c) NXP B.V. 2008. All rights reserved.
00*
x
R/W
0*
Product data sheet
Rev. 01 -- 20 May 2008
90 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 101. CH_STAT_B_x channel status bytes 0, 1, 3 and 4 registers (address 14h to 17h) bit description Legend: * = default value Address Register Bit Symbol Access Value Description channel status byte x: x = 0 to 4 14h 15h 16h 17h CH_STAT_B_0 CH_STAT_B_1 CH_STAT_B_3 CH_STAT_B_4 7 to 0 7 to 0 7 to 0 7 to 0 CH_STAT_BYTE_0[7:0] CH_STAT_BYTE_1[7:0] CH_STAT_BYTE_3[7:0] CH_STAT_BYTE_4[7:0] R/W R/W R/W R/W 00h* 00h* 00h* 00h* byte 0 byte 1 byte 3 byte 4
Table 102. CH_STAT_B_2_APx_n channel status byte 2 registers (address 18h to 1Fh) bit description Legend: * = default value Address Register Bit Symbol Access Value Description channel status byte 2 of audio port x: x = 0 to 3 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh CH_STAT_B_2_AP0_L CH_STAT_B_2_AP0_R CH_STAT_B_2_AP1_L CH_STAT_B_2_AP1_R CH_STAT_B_2_AP2_L CH_STAT_B_2_AP2_R CH_STAT_B_2_AP3_L CH_STAT_B_2_AP3_R 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 7 to 0 CH_STAT_BYTE_2_AP0_L[7:0] CH_STAT_BYTE_2_AP0_R[7:0] CH_STAT_BYTE_2_AP1_L[7:0] CH_STAT_BYTE_2_AP1_R[7:0] CH_STAT_BYTE_2_AP2_L[7:0] CH_STAT_BYTE_2_AP2_R[7:0] CH_STAT_BYTE_2_AP3_L[7:0] CH_STAT_BYTE_2_AP3_R[7:0] R/W R/W R/W R/W R/W R/W R/W R/W 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* audio port 0 left audio port 0 right audio port 1 left audio port 1 right audio port 2 left audio port 2 right audio port 3 left audio port 3 right
9.7.2 ISRC packets registers
Below is an example of use. Please refer to HDMI 1.2a specification for the correct definition of data bytes. See HDMI 1.2a specification, section 8.8 for rules regarding the use of the ISRC packets.
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description Legend: * = default value Address Register 20h 21h ISRC1_PACKET_ TYPE ISRC1_CTRL Bit Symbol Access Value Description 05h* 0* 0* 000* 000* 001 010 100 ISRC1 packet type: packet type of the ISRC1 packet ISRC continued: ISRC continued in next packet ISRC valid: ISRC status and data are valid ISRC1 reserved: reserved (shall be zero) ISRC status starting position intermediate position ending position 7 to 0 ISRC1_PACKET_TYPE[7:0] R/W 7 6 ISRC_CONT ISRC_VALID R/W R/W R/W R/W
5 to 3 ISRC1_RSVD[5:3] 2 to 0 ISRC_STATUS[2:0]
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
91 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 103. ISRC1 packet registers (address 20h to 3Eh) bit description ...continued Legend: * = default value Address Register 22h ISRC1_RSVD Bit Symbol Access Value Description R/W 00h* ISRC1 reserved: reserved (shall be zero) ISRC1 data byte x: x = 0 to 15 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh
TDA9983B_1
7 to 0 ISRC1_RSVD[7:0]
UPC_EAN_ISRC_0 UPC_EAN_ISRC_1 UPC_EAN_ISRC_2 UPC_EAN_ISRC_3 UPC_EAN_ISRC_4 UPC_EAN_ISRC_5 UPC_EAN_ISRC_6 UPC_EAN_ISRC_7 UPC_EAN_ISRC_8 UPC_EAN_ISRC_9
7 to 0 UPC_EAN_ISRC_0[7:0] 7 to 0 UPC_EAN_ISRC_1[7:0] 7 to 0 UPC_EAN_ISRC_2[7:0] 7 to 0 UPC_EAN_ISRC_3[7:0] 7 to 0 UPC_EAN_ISRC_4[7:0] 7 to 0 UPC_EAN_ISRC_5[7:0] 7 to 0 UPC_EAN_ISRC_6[7:0] 7 to 0 UPC_EAN_ISRC_7[7:0] 7 to 0 UPC_EAN_ISRC_8[7:0] 7 to 0 UPC_EAN_ISRC_9[7:0]
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h*
UPC/EAN or ISRC byte 0 UPC/EAN or ISRC byte 1 UPC/EAN or ISRC byte 2 UPC/EAN or ISRC byte 3 UPC/EAN or ISRC byte 4 UPC/EAN or ISRC byte 5 UPC/EAN or ISRC byte 6 UPC/EAN or ISRC byte 7 UPC/EAN or ISRC byte 8 UPC/EAN or ISRC byte 9 UPC/EAN or ISRC byte 10 UPC/EAN or ISRC byte 11 UPC/EAN or ISRC byte 12 UPC/EAN or ISRC byte 13 UPC/EAN or ISRC byte 14 UPC/EAN or ISRC byte 15 ISRC1 data byte x: x = 16 to 27 reserved byte 16 (shall be set to a value of 0) reserved byte 17 (shall be set to a value of 0) reserved byte 18 (shall be set to a value of 0) reserved byte 19 (shall be set to a value of 0) reserved byte 20 (shall be set to a value of 0) reserved byte 21 (shall be set to a value of 0) reserved byte 22 (shall be set to a value of 0) reserved byte 23 (shall be set to a value of 0) reserved byte 24 (shall be set to a value of 0) reserved byte 25 (shall be set to a value of 0) reserved byte 26 (shall be set to a value of 0) reserved byte 27 (shall be set to a value of 0)
(c) NXP B.V. 2008. All rights reserved.
UPC_EAN_ISRC_10 7 to 0 UPC_EAN_ISRC_10[7:0] UPC_EAN_ISRC_11 7 to 0 UPC_EAN_ISRC_11[7:0] UPC_EAN_ISRC_12 7 to 0 UPC_EAN_ISRC_12[7:0] UPC_EAN_ISRC_13 7 to 0 UPC_EAN_ISRC_13[7:0] UPC_EAN_ISRC_14 7 to 0 UPC_EAN_ISRC_14[7:0] UPC_EAN_ISRC_15 7 to 0 UPC_EAN_ISRC_15[7:0] ISRC1_PB16 ISRC1_PB17 ISRC1_PB18 ISRC1_PB19 ISRC1_PB20 ISRC1_PB21 ISRC1_PB22 ISRC1_PB23 ISRC1_PB24 ISRC1_PB25 ISRC1_PB26 ISRC1_PB27 7 to 0 ISRC1_PB_BYTE_16[7:0] 7 to 0 ISRC1_PB_BYTE_17[7:0] 7 to 0 ISRC1_PB_BYTE_18[7:0] 7 to 0 ISRC1_PB_BYTE_19[7:0] 7 to 0 ISRC1_PB_BYTE_20[7:0] 7 to 0 ISRC1_PB_BYTE_21[7:0] 7 to 0 ISRC1_PB_BYTE_22[7:0] 7 to 0 ISRC1_PB_BYTE_23[7:0] 7 to 0 ISRC1_PB_BYTE_24[7:0] 7 to 0 ISRC1_PB_BYTE_25[7:0] 7 to 0 ISRC1_PB_BYTE_26[7:0] 7 to 0 ISRC1_PB_BYTE_27[7:0]
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description Legend: * = default value Address Register 40h 41h 42h ISRC2_PACKET_ TYPE ISRC2_RSVD1 ISRC2_RSVD2 Bit Symbol Access Value Description 06h* 00h* 00h* ISRC2 packet type: packet type of the ISRC2 packet ISRC2 reserved 1: reserved (shall be zero) ISRC2 reserved 2: reserved (shall be zero) ISRC2 data byte x: x = 0 to 15 43h 44h 45h 46h 47h 48h 49h 4Ah 4Bh 4Ch 4Dh 4Eh 4Fh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh UPC_EAN_ISRC_16 7 to 0 UPC_EAN_ISRC_16[7:0] UPC_EAN_ISRC_17 7 to 0 UPC_EAN_ISRC_17[7:0] UPC_EAN_ISRC_18 7 to 0 UPC_EAN_ISRC_18[7:0] UPC_EAN_ISRC_19 7 to 0 UPC_EAN_ISRC_19[7:0] UPC_EAN_ISRC_20 7 to 0 UPC_EAN_ISRC_20[7:0] UPC_EAN_ISRC_21 7 to 0 UPC_EAN_ISRC_21[7:0] UPC_EAN_ISRC_22 7 to 0 UPC_EAN_ISRC_22[7:0] UPC_EAN_ISRC_23 7 to 0 UPC_EAN_ISRC_23[7:0] UPC_EAN_ISRC_24 7 to 0 UPC_EAN_ISRC_24[7:0] UPC_EAN_ISRC_25 7 to 0 UPC_EAN_ISRC_25[7:0] UPC_EAN_ISRC_26 7 to 0 UPC_EAN_ISRC_26[7:0] UPC_EAN_ISRC_27 7 to 0 UPC_EAN_ISRC_27[7:0] UPC_EAN_ISRC_28 7 to 0 UPC_EAN_ISRC_28[7:0] UPC_EAN_ISRC_29 7 to 0 UPC_EAN_ISRC_29[7:0] UPC_EAN_ISRC_30 7 to 0 UPC_EAN_ISRC_30[7:0] UPC_EAN_ISRC_31 7 to 0 UPC_EAN_ISRC_31[7:0] ISRC2_PB16 ISRC2_PB17 ISRC2_PB18 ISRC2_PB19 ISRC2_PB20 ISRC2_PB21 ISRC2_PB22 ISRC2_PB23 ISRC2_PB24 7 to 0 ISRC2_PB_BYTE_16[7:0] 7 to 0 ISRC2_PB_BYTE_17[7:0] 7 to 0 ISRC2_PB_BYTE_18[7:0] 7 to 0 ISRC2_PB_BYTE_19[7:0] 7 to 0 ISRC2_PB_BYTE_20[7:0] 7 to 0 ISRC2_PB_BYTE_21[7:0] 7 to 0 ISRC2_PB_BYTE_22[7:0] 7 to 0 ISRC2_PB_BYTE_23[7:0] 7 to 0 ISRC2_PB_BYTE_24[7:0] R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* 00h* UPC/EAN or ISRC byte 16 UPC/EAN or ISRC byte 17 UPC/EAN or ISRC byte 18 UPC/EAN or ISRC byte 19 UPC/EAN or ISRC byte 20 UPC/EAN or ISRC byte 21 UPC/EAN or ISRC byte 22 UPC/EAN or ISRC byte 23 UPC/EAN or ISRC byte 24 UPC/EAN or ISRC byte 25 UPC/EAN or ISRC byte 26 UPC/EAN or ISRC byte 27 UPC/EAN or ISRC byte 28 UPC/EAN or ISRC byte 29 UPC/EAN or ISRC byte 30 UPC/EAN or ISRC byte 31 ISRC2 data byte x: x = 16 to 27 reserved byte 16 (shall be set to a value of 0) reserved byte 17 (shall be set to a value of 0) reserved byte 18 (shall be set to a value of 0) reserved byte 19 (shall be set to a value of 0) reserved byte 20 (shall be set to a value of 0) reserved byte 21 (shall be set to a value of 0) reserved byte 22 (shall be set to a value of 0) reserved byte 23 (shall be set to a value of 0) reserved byte 24 (shall be set to a value of 0) 7 to 0 ISRC2_PACKET_TYPE[7:0] R/W 7 to 0 ISRC2_RSVD1[7:0] 7 to 0 ISRC2_RSVD2[7:0] R/W R/W
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 104. ISRC2 packet registers (address 40h to 5Eh) bit description ...continued Legend: * = default value Address Register 5Ch 5Dh 5Eh ISRC2_PB25 ISRC2_PB26 ISRC2_PB27 Bit Symbol Access Value Description R/W R/W R/W 00h* 00h* 00h* reserved byte 25 (shall be set to a value of 0) reserved byte 26 (shall be set to a value of 0) reserved byte 27 (shall be set to a value of 0) 7 to 0 ISRC2_PB_BYTE_25[7:0] 7 to 0 ISRC2_PB_BYTE_26[7:0] 7 to 0 ISRC2_PB_BYTE_27[7:0]
9.7.3 Audio content protection packet registers
Below is an example of use. Please refer to HDMI 1.2a specification for the correct definition of data bytes. See HDMI 1.2a specification, section 9.3 for rules regarding the use of ACP packets.
Table 105. ACP packet registers (address 60h to 7Eh) bit description Legend: * = default value Address Register 60h ACP_ PACKET_ TYPE ACP_TYPE ACP_RSVD ACP_PB0 Bit Symbol Access Value R/W 04h* Description audio content protection packet type: packet type of the audio content protection packet audio content protection type: content protection type audio content protection reserved: reserved (shall be zero) audio content protection data byte 0 ACP_TYPE = 2: DVD-audio DVD-Audio_Type_Dependent_ Generation [8 bits] identifies the generation of the DVD-Audio-specific ACP_Type_ Dependent fields. Shall be set to logic 1. ACP_TYPE = 3: super audio CD CCI_1_b0[7:0] 7 to 0 ACP_PACKET_ TYPE[7:0] 7 to 0 ACP_TYPE[7:0] 7 to 0 ACP_RSVD[7:0] 7 to 0 ACP_PB_BYTE_0[7:0]
61h 62h 63h
R/W R/W R/W
00h* 00h* 00h*
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 105. ACP packet registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 64h ACP_PB1 Bit Symbol Access Value R/W 00* Description audio content protection data byte 1 7 to 6 ACP_PB_BYTE_1[7:6] ACP_TYPE = 2: DVD audio Copy_Permission[1:0] = audio_copy_permission parameter ACP_TYPE = 3: super audio CD CCI_1_b1[7:6] 5 to 3 ACP_PB_BYTE_1[5:3] R/W 000* ACP_TYPE = 2: DVD audio Copy_Number[2:0] = audio_copy_number parameter ACP_TYPE = 3: super audio CD CCI_1_b1[5:3] 2 to 1 ACP_PB_BYTE_1[2:1] R/W 00* ACP_TYPE = 2: DVD audio Quality[1:0] = audio_quality parameter ACP_TYPE = 3: super audio CD CCI_1_b1[2:1] 0 ACP_PB_BYTE_1[0] R/W 0* ACP_TYPE = 2: DVD audio Transaction = audio_transaction parameter ACP_TYPE = 3: super audio CD CCI_1_b1[0] 65h ACP_PB2 7 to 0 ACP_PB_BYTE_2[7:0] R/W 00h* audio content protection data byte 2 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b2[7:0] 66h ACP_PB3 7 to 0 ACP_PB_BYTE_3[7:0] R/W 00h* audio content protection data byte 3 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b3[7:0] 67h ACP_PB4 7 to 0 ACP_PB_BYTE_4[7:0] R/W 00h* audio content protection data byte 4 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b4[7:0] 68h ACP_PB5 7 to 0 ACP_PB_BYTE_5[7:0] R/W 00h* audio content protection data byte 5 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b5[7:0]
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 105. ACP packet registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 69h ACP_PB6 Bit Symbol Access Value R/W 00h* Description audio content protection data byte 6 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b6[7:0] 6Ah ACP_PB7 7 to 0 ACP_PB_BYTE_7[7:0] R/W 00h* audio content protection data byte 7 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b7[7:0] 6Bh ACP_PB8 7 to 0 ACP_PB_BYTE_8[7:0] R/W 00h* audio content protection data byte 8 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b8[7:0] 6Ch ACP_PB9 7 to 0 ACP_PB_BYTE_9[7:0] R/W 00h* audio content protection data byte 9 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b9[7:0] 6Dh ACP_PB10 7 to 0 ACP_PB_BYTE_10[7:0] R/W 00h* audio content protection data byte 10 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b10[7:0] 6Eh ACP_PB11 7 to 0 ACP_PB_BYTE_11[7:0] R/W 00h* audio content protection data byte 11 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b11[7:0] 6Fh ACP_PB12 7 to 0 ACP_PB_BYTE_12[7:0] R/W 00h* audio content protection data byte 12 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b12[7:0] 70h ACP_PB13 7 to 0 ACP_PB_BYTE_13[7:0] R/W 00h* audio content protection data byte 13 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b13[7:0] 7 to 0 ACP_PB_BYTE_6[7:0]
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 105. ACP packet registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 71h ACP_PB14 Bit Symbol Access Value R/W 00h* Description audio content protection data byte 14 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b14[7:0] 72h ACP_PB15 7 to 0 ACP_PB_BYTE_15[7:0] R/W 00h* audio content protection data byte 15 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b15[7:0] 73h ACP_PB16 7 to 0 ACP_PB_BYTE_16[7:0] R/W 00h* audio content protection data byte 16 ACP_TYPE = 2: DVD audio reserved (0) ACP_TYPE = 3: super audio CD CCI_1_b16[7:0] 74h ACP_PB17 7 to 0 ACP_PB_BYTE_17[7:0] R/W 00h* audio content protection data byte 17 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 75h ACP_PB18 7 to 0 ACP_PB_BYTE_18[7:0] R/W 00h* audio content protection data byte 18 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 76h ACP_PB19 7 to 0 ACP_PB_BYTE_19[7:0] R/W 00h* audio content protection data byte 19 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 77h ACP_PB20 7 to 0 ACP_PB_BYTE_20[7:0] R/W 00h* audio content protection data byte 20 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 78h ACP_PB21 7 to 0 ACP_PB_BYTE_21[7:0] R/W 00h* audio content protection data byte 21 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 79h ACP_PB22 7 to 0 ACP_PB_BYTE_22[7:0] R/W 00h* audio content protection data byte 22 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7 to 0 ACP_PB_BYTE_14[7:0]
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TDA9983B
150 MHz pixel rate HDMI transmitter
Table 105. ACP packet registers (address 60h to 7Eh) bit description ...continued Legend: * = default value Address Register 7Ah ACP_PB23 Bit Symbol Access Value R/W 00h* Description audio content protection data byte 23 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7Bh ACP_PB24 7 to 0 ACP_PB_BYTE_24[7:0] R/W 00h* audio content protection data byte 24 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7Ch ACP_PB25 7 to 0 ACP_PB_BYTE_25[7:0] R/W 00h* audio content protection data byte 25 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7Dh ACP_PB26 7 to 0 ACP_PB_BYTE_26[7:0] R/W 00h* audio content protection data byte 26 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7Eh ACP_PB27 7 to 0 ACP_PB_BYTE_27[7:0] R/W 00h* audio content protection data byte 27 ACP_TYPE = 2: DVD audio or ACP_TYPE = 3: super audio CD reserved (0) 7 to 0 ACP_PB_BYTE_23[7:0]
9.7.4 Current page address register
Table 106. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol Access Value Description 00h* current page address: selects the current memory page CURPAGE_ADR[7:0] W
9.8 HDMI and DVI page register definitions
The current page address for the HDMI and DVI page is 12h. The configuration of the registers for this page is given in Table 107.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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NXP Semiconductors
Table 107. I2C-bus registers of memory page 12h[1] Register Not used : Not used HDCP_TX33 Not used : Not used CURPAGE_ADR
[1]
Sub R/W addr 00h : B7h B8h B9h : FEh FFh : R/W : W
Bit 7 (MSB) 6 5 4 : x x x x : CURPAGE_ADR[7:0] x x HDMI x 3 2 1 0 (LSB)
Default value 0000 0000 : 0000 0000 0000 0000 0000 0000 : 0000 0000 0000 0000
R: reading register W: writing register x: bit must be set to default value for proper operation -: not used
150 MHz pixel rate HDMI transmitter
TDA9983B
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NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
9.8.1 HDMI control registers
Table 108. HDCP_TX33 register (address B8h) bit description Legend: * = default value Bit 7 to 6 1 Symbol x HDMI Access Value R/W R/W 0* 1 0 x R/W 0* Description HDMI DVI mode HDMI mode undefined 0000 00* undefined
9.8.2 Current page address register
Table 109. CURPAGE_ADR register (address FFh) bit description Legend: * = default value Bit 7 to 0 Symbol CURPAGE_ADR[7:0] Access Value W 00h* Description current page address: selects the current memory page
10. Limiting values
Table 110. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD(3V3) VDD(1V8) VDD Tstg Tamb Tj Vesd Parameter supply voltage (3.3 V) supply voltage (1.8 V) supply voltage difference storage temperature ambient temperature junction temperature electrostatic discharge voltage HBM Conditions Min -0.5 -0.5 -0.5 -55 0 -1500 Max +4.6 +2.5 +0.5 +150 70 125 +1500 Unit V V V C C C V
11. Thermal characteristics
Table 111. Thermal characteristics Symbol Rth(j-a) Rth(j-c) Parameter thermal resistance from junction to ambient thermal resistance from junction to case Conditions in free air; JEDEC 4L board Typ 26.5 10.2 Unit K/W K/W
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150 MHz pixel rate HDMI transmitter
12. Static characteristics
Table 112. Supplies VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol VDDA(FRO_3V3) VDDA(PLL_3V3) VDDH(3V3) VDDD(3V3) VDDC(1V8) IDDA(FRO_3V3) IDDA(PLL_3V3) IDDD(3V3) IDDH(3V3) IDDC(1V8) fclk(max) Pcons Ptot Ppd IDDA(FRO_3V3) IDDA(PLL_3V3) IDDD(3V3) IDDH(3V3) IDDC(1V8) fclk(max) Pcons Ptot Ppd
[1] [2]
Parameter free running oscillator 3.3 V analog supply voltage PLL 3.3 V analog supply voltage HDMI supply voltage (3.3 V) digital supply voltage (3.3 V) core supply voltage (1.8 V) free running oscillator 3.3 V analog supply current PLL 3.3 V analog supply current digital supply current (3.3 V) HDMI supply current (3.3 V) core supply current (1.8 V) maximum clock frequency power consumption
Conditions
Min 3.0 3.0 3.0
[1] [1]
Typ 3.3 3.3 3.3 3.3 1.8 0 4.5 14 154.5 322 338 458 472 13.5 0 4 14 167 361 495 13.5
Max 3.6 3.6 3.6 3.6 1.95 1 6 5 16.5 200 503 651 38.4 1 5 5 16.5 210 583 732 38.4
Unit V V V V V mA mA mA mA mA MHz mW mW mW mW mW mA mA mA mA mA MHz mW mW mW
TDA9983BHW/8 and TDA9983BHW/15
3.0 1.65 -
TDA9983BHW/8; up to 81 MHz
[2]
-
[2] [3] [3]
81 -
worst case total power dissipation worst case power dissipation in power-down mode free running oscillator 3.3 V analog supply current PLL 3.3 V analog supply current digital supply current (3.3 V) HDMI supply current (3.3 V) core supply current (1.8 V) maximum clock frequency power consumption total power dissipation power dissipation in power-down mode TDA9983BHW/15; up to 150 MHz
[2] [3] [2]
[4]
-
[4] [4] [4] [4]
150 -
The VDDD(3V3) and VDDC(1V8) power supplies must always follow the sequence shown in Figure 14 to ensure proper power-up conditions. Worst case video format: a) Input 480p (YCBCR 4 : 2 : 2 semi-planar) b) Output 720p (YCBCR 4 : 2 : 2) Video format: a) Input 480p (ITU656 embedded sync, rising edge) b) Output 1080i (YCBCR 4 : 2 : 2) Video format: a) Input 1080p (RGB 4 : 4 : 4 external sync, rising edge)
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[3]
[4]
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TDA9983B
150 MHz pixel rate HDMI transmitter
b) Output 1080p (RGB 4 : 4 : 4)
Table 113. LV-TTL digital inputs and outputs VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE and RST_N VIL VIH IIL IIH Ci VIL VIH Ci VOL LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage CL = 10 pF; IOL = 2 mA 2.0 -1 -1 2.0 4.5 4.5 0.8 +1 +1 0.8 0.4 V V A A pF V V pF V
5 V tolerant input: pin HPD
Output: pin INT
Table 114. TMDS outputs VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol Vo(p-p) VOH VOL Parameter Conditions Min 400 3.125 2.535 Typ 525 3.3 2.8 Max 600 3.475 3.065 Unit mV V V TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2-, TX2+, TXC- and TXC+ peak-to-peak output voltage single output; Rext = 610 (1 % tolerance) with test load and operating condition as in HIGH-level output voltage HDMI 1.2a specification LOW-level output voltage
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150 MHz pixel rate HDMI transmitter
13. Dynamic characteristics
Table 115. Timing characteristics VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 70 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol td fclk(max) tsu(D) th(D) clk DDC fSCL I2C-bus; fSCL Parameter delay time maximum clock frequency data input set-up time data input hold time clock duty cycle I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL standard mode standard mode fast mode TMDS output pins: TXC- and TXC+ fclk(max) maximum clock frequency TDA9983BHW/8 TDA9983BHW/15 TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2- and TX2+ fclk(max) maximum clock frequency TDA9983BHW/8 TDA9983BHW/15 810 1.5 MHz GHz 81 150 MHz MHz 100 100 400 kHz kHz kHz SCL clock frequency SCL clock frequency TDA9983BHW/8 TDA9983BHW/15 Conditions Min 1 81 150 -1.3 3.6 40 Typ Max 60 Unit ms MHz MHz ns ns % Supplies: pins VDDC(1V8), VDDD(3V3); see Figure 14 Clock inputs: pins VCLK, VPA[7:0], VPB[7:0], VPC[7:0]; see Figure 15, 16, 17, 18 and 19
5 V tolerant; master bus: pins I2C_SDA and I2C_SCL
3.3 V
1.8 V
50 %
27 %
td 0 s
001aag259
Fig 14. Power supply sequencing
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150 MHz pixel rate HDMI transmitter
13.1 Input format
In Table 116 the port VPA has been mapped to CB (YUV space)/B (RGB space), VPB has been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to CR (YUV space)/R (RGB space).
Table 116. Input format Input pins Video port A VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Video port C VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7]
[1] [2] [3] [4]
Signal
RGB 4:4: 4[1]
YUV 4 : 4 : 4[2] CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] CR[0] CR[1] CR[2] CR[3] CR[4] CR[5] CR[6] CR[7] 4 : 2 : 2 (semi-planar)[3] Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] 4 : 2 : 2: (ITU656-like)[4] CB[0] CB[1] CB[2] CB[3] L L L L CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] Y0[0] Y0[1] Y0[2] Y0[3] L L L L Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[0] CR[1] CR[2] CR[3] L L L L CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[0] Y1[1] Y1[2] Y1[3] L L L L Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9]
CB[0]/B[0] CB[1]/B[1] CB[2]/B[2] CB[3]/B[3] CB[4]/B[4] CB[5]/B[5] CB[6]/B[6] CB[7]/B[7] Y[0]/G[0] Y[1]/G[1] Y[2]/G[2] Y[3]/G[3] Y[4]/G[4] Y[5]/G[5] Y[6]/G[6] Y[7]/G[7] CR[0]/R[0] CR[1]/R[1] CR[2]/R[2] CR[3]/R[3] CR[4]/R[4] CR[5]/R[5] CR[6]/R[6] CR[7]/R[7]
B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7]
CB[10] Y0[10] CR[10] Y1[10] CB[11] Y0[11] CR[11] Y1[11] L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
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13.2 Example of supported video
The TDA9983B supports all EIA/CEA-861B, ATSC video input formats.
Table 117. Timing parameters for EIA/CEA-861B Format nr. Format V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler (Hz) (kHz) (MHz) 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 60 60 60 60 60 60 60 60 60 60 60 60 50 50 50 50 50 50 800 858 1650 2200 858 858 858 858 858 858 1716 2200 800 858 1650 2200 858 858 858 858 858 858 1716 2200 864 1980 2640 864 864 864 525 525 750 1125 525 262 263 525 262 263 525 1125 525 525 750 1125 525 262 263 525 262 263 525 1125 625 750 1125 625 312 313 31.4685 31.4685 44.955 33.7163 15.7343 15.7043 15.7642 15.7343 15.7043 15.7642 31.4685 67.4326 31.5 31.5 45 33.75 15.75 15.72 15.78 15.75 15.72 15.78 31.5 67.5 31.25 37.5 28.125 15.625 15.6 15.65 25.174825 27 74.175824 74.175824 13.5 13.474286 13.525714 13.5 13.474286 13.525714 54 148.35165[1] 25.2 27.27 74.25 74.25 13.5135 13.48776 13.53924 13.5135 13.48776 13.53924 54.054 148.5[1] 27 74.25 74.25 13.5 13.4784 13.5216 1 1 1 1 2 2 2 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 1 2 2 2 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 1 2 2 X X X X X X (c) NXP B.V. 2008. All rights reserved.
59.94 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16[1] 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16[1] 17, 18 19 20 21, 22 (PAL) 23, 24 23, 24
TDA9983B_1
640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 720 x 480i 720 x 240p 720 x 240p 720 x 480i 720 x 240p 720 x 240p 1440 x 480p 1920 x 1080p 640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 720 x 480i 720 x 240p 720 x 240p 720 x 480i 720 x 240p 720 x 240p 1440 x 480p 1920 x 1080p 720 x 576p 1280 x 720p 1920 x 1080i 720 x 576i 720 x 288p 720 x 288p
60 Hz systems
50 Hz systems
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150 MHz pixel rate HDMI transmitter
Table 117. Timing parameters for EIA/CEA-861B ...continued Format nr. 23, 24 25, 26 27, 28 27, 28 27, 28 29, 30 31[1] 32 32 33 34 34
[1]
Format 720 x 288p 720 x 576i 720 x 288p 720 x 288p 720 x 288p 1440 x 576p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p
V frequency H total V total H frequency Pixel frequency Pixel repetition Scaler (Hz) (kHz) (MHz) 50 50 50 50 50 50 50 23.976 24 25 29.97 30 864 864 864 864 864 1728 2640 2750 2750 2640 2200 2200 314 625 312 313 314 625 1125 1125 1125 1125 1125 1125 15.7 15.625 15.6 15.65 15.7 31.25 56.25 26.973 27 28.125 33.716 33.75 13.5648 13.5 13.4784 13.5216 13.5648 54 148.5[1] 74.175824 74.25 74.25 74.175824 74.25 2 4, 5, 10[1] 7[1], 8[1], -
4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 1 1 1
Various systems
Only for TDA9983BHW/15.
Table 118. Timing parameters for PC standards below 150 MHz Standard VGA Format 640 x 350p 640 x 400p 720 x 400p 640 x 480p 640 x 480p 640 x 480p 640 x 480p SVGA 800 x 600p 800 x 600p 800 x 600p 800 x 600p 800 x 600p V frequency (Hz) 85.08 85.08 85.039 59.94005994 72.809 75 85.008 56.250 60.317 72.188 75.000 85.061 H total V total H frequency Pixel frequency (kHz) (MHz) 832 832 936 800 832 840 832 1024 1056 1040 1056 1048 445 445 446 525 520 500 509 625 628 666 625 631 37.8606 37.8606 37.927394 37.86068 37.5 43.269072 35.15625 37.879076 48.077208 46.875 53.673491 31.5000192 31.5000192 35.50004078 31.50008576 31.5 35.9998679 36 40.00030426 50.00029632 49.5 56.24981857 Pixel repetition Scaler -
31.46853147 25.17482517
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150 MHz pixel rate HDMI transmitter
Table 118. Timing parameters for PC standards below 150 MHz ...continued Standard XGA Format 1024 x 786p 1024 x 786p 1024 x 786p 1024 x 786p[1] 1024 x 786i 1152 x 1152 x 864p[1] 864p[1] V frequency (Hz) 60.004 70.069 75.029 84.997 86.957 75.000 84.999 60 85.002 60.020 75.025 H total V total H frequency Pixel frequency (kHz) (MHz) 1344 1328 1312 1376 1264 1600 1576 1800 1728 1688 1688 806 806 800 808 817 900 907 1000 1011 1066 1066 48.363224 56.475614 60.0232 68.677576 35.5219345 67.5 77.094093 60 85.937022 63.98132 79.97665 65.00017306 74.99961539 78.7504384 94.50034458 44.89972521 108 121.5002906 108 148.499174 108.0004682 135.0005852 Pixel repetition Scaler -
1280 x 960p[1] 1280 x 960p[1] SXGA[1] 1280 x 1280 x
[1]
1024p[1] 1024p[1]
Only for TDA9983BHW/15.
13.3 Timing diagrams
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0 B1 B2 B3 ... Bxxx Bxxx
VPB[7:0]
G0
G1
G2
G3
...
Gxxx
Gxxx
VPC[7:0]
R0 th(D) tsu(D)
R1
R2
R3
...
Rxxx
Rxxx
001aag250
Fig 15. Timing in RGB 4 : 4 : 4 (rising edge) input
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150 MHz pixel rate HDMI transmitter
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] CB0 CB1 CB2 CB3 ... CBxxx CBxxx
VPB[7:0]
Y0
Y1
Y2
Y3
...
Yxxx
Yxxx
VPC[7:0]
CR0 th(D) tsu(D)
CR1
CR2
CR3
...
CRxxx
CRxxx
001aag251
Fig 16. Timing in YCBCR 4 : 4 : 4 (rising edge) input
VCLK tclk(H) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF C B0 th(D) tsu(D) tsu(D) Y0 CR0 Y1 th(D)
001aag252
tclk(L)
VPB[7:0]; VPA[3:0]
...
CRxxx
Yxxx
Fig 17. Timing YCBCR 4 : 2 : 2 ITU656-like double edge (rising and falling) input
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF CB0 th(D) tsu(D)
001aag253
VPB[7:0]; VPA[3:0]
Y0
CR0
Y1
...
CRxxx
Yxxx
Fig 18. Timing YCBCR 4 : 2 : 2 ITU656-like single edge external (rising edge) input
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150 MHz pixel rate HDMI transmitter
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF Y0 Y1 Y2 Y3 Y4 Y5 ... th(D)
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
C B0
C R0
CB2 tsu(D)
CR2
CB4
CR4
...
001aag256
Fig 19. Timing YCBCR 4 : 2 : 2 semi-planar external synchronization (rising edge) input
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150 MHz pixel rate HDMI transmitter
14. Application information
DAC DENC G ADC DSP DAC
CVBS/Y/(G)
C/PB/(B) PR/(R)
8
LO
audio I2S-bus or S/PDIF
AUX data
DAC
HDMI TX
HDMI data stream
STEREO AUDIO DAC
001aaf298
Fig 20. Application diagram for Set-Top Box
DAC DVD READ ENGINE DENC DSP DAC
CVBS/Y/(G)
C/PB/(B) PR/(R)
audio I2S-bus or S/PDIF
DAC AUX data SCALER HDMI TX
8
HDMI data stream
STEREO AUDIO DAC
001aaf299
Fig 21. Application diagram for DVD player
reset digital video (up to 24 bits) MICROPROCESSOR MASTER MPEG2 DECODER sync signals audio, S/PDIF and I2S-bus IRQ I2C-bus MASTER SLAVE I2C-bus MASTER HDMI
HDMI clock HDMI channel 0 HDMI channel 1 HDMI channel 2 hot plug detect DDC (SCL and SDA) SLAVE E-EDID SLAVE ADDRESS A0 CEC line
001aag260
TDA9983B
HDMI RECEIVER/ REPEATER
HDMI SOURCE
Fig 22. Transmitter connection with external world
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150 MHz pixel rate HDMI transmitter
15. Package outline
HTQFP80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad SOT841-4
c y exposed die pad X
Dh 60 61 41 40 ZE
A
e Eh w bp
M
E
HE
A A2
(A 3) A1 detail X L Lp
pin 1 index 80 1 w D HD
M
21 20 ZD B v
M
v
M
A
e
bp
B
0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.15 0.05 A2 1.05 0.95 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 12.1 11.9 Dh 4.79 4.69 E (1) 12.1 11.9 Eh 4.79 4.69
5 scale
10 mm
e 0.5
HD
HE
L 1
Lp 0.75 0.45
v 0.2
w 0.08
y 0.1
ZD(1) ZE(1) 1.45 1.05 1.45 1.05
7 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included OUTLINE VERSION SOT841-4 REFERENCES IEC JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 06-04-25 06-06-20
Fig 23. Package outline SOT841-4 (HTQFP80)
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16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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150 MHz pixel rate HDMI transmitter
16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 24) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 119 and 120
Table 119. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 235 220 350 220 220
Table 120. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 24.
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150 MHz pixel rate HDMI transmitter
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 24. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Soldering: additional information
The package of this device supports the reflow soldering process only.
18. Abbreviations
Table 121. Abbreviations Acronym AAC AC-3 ACP ADC AFD ATRAC AV CEC CMOS CTS DAC DDC DENC DSC DSP DTS
TDA9983B_1
Description Advanced Audio Coding Active Coding-3 Audio Content Protection Analog-to-Digital Converter Active Format Descriptor Adaptive TRansform Acoustic Coding Audio Video Consumer Electronic Control Complimentary Metal-Oxide Semiconductor Cycle Time Stamp Digital-to-Analog Converter Display Data Channel Digital video ENCoder Distributed Source Code Digital Signal Processor Digital Transmission System
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150 MHz pixel rate HDMI transmitter
Table 121. Abbreviations ...continued Acronym DVB DVC DVD DVI D-VHS EAV EDID ROM E-EDID FIFO HBM HDCP HDD HDMI HDTV HPD ID IRQ ISRC KSV LO L-PCM LSB LUT LV-TTL MSB PAL PCM PLL PVR RGB Rx SAV STB S/PDIF TMDS Tx UPC/EAN YUV YCBCR Description Digital Video Broadcast Digital Video Camera Digital Versatile Disc Digital Visual Interface Data-VHS End Active Video Extended Display Identification Data ROM Enhanced Extended Display Identification Data First In First Out Human Body Model High-bandwidth Digital Content Protection Hard-Disk Drive High-Definition Multimedia Interface High-Definition Television Hot Plug Detect Identifier Interrupt ReQuest International Standard Recording Code Key Selection Vector Local Oscillator Linear Pulse Code Modulation Least Significant Bit Look-Up Table Low Voltage Transistor-Transistor Logic Most Significant Bit Phase Alternating Line Pulse-Code Modulation Phase-Locked Loop Personal Video Recorder Red Green Blue Receiver Start Active Video Set-Top Box Sony/Philips Digital Interface Transition Minimized Differential Signalling Transmitter Universal Product Code/European Assistance Network (GS1) Y = luminance, U = normalized blue, V = normalized red Y = luminance, CB = chroma component blue, CR = chroma component red
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19. Revision history
Table 122. Revision history Document ID TDA9983B_1 Release date 20080520 Data sheet status Product data sheet Change notice Supersedes -
TDA9983B_1
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150 MHz pixel rate HDMI transmitter
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
117 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 Video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 Timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 Data enable generator . . . . . . . . . . . . . . . . . . 18 8.4 Input and output video format . . . . . . . . . . . . . 18 8.5 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 Color space converter. . . . . . . . . . . . . . . . . . . 19 8.7 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 Audio input format. . . . . . . . . . . . . . . . . . . . . . 19 8.9 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11 Power management . . . . . . . . . . . . . . . . . . . . 20 8.12 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 8.13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.14 HDMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.1 Output HDMI buffers . . . . . . . . . . . . . . . . . . . . 21 8.14.2 Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.3 HDMI and DVI receiver discrimination . . . . . . 21 8.14.4 DDC channel . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.4.1 E-EDID reading. . . . . . . . . . . . . . . . . . . . . . . . 21 8.15 Scaler unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.16 Input and output video scaler . . . . . . . . . . . . . 22 8.17 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 22 2C-bus register definitions . . . . . . . . . . . . . . . 23 9 I 9.1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 Memory page management . . . . . . . . . . . . . . 23 9.3 General control page register definitions . . . . 23 9.3.1 Main control register . . . . . . . . . . . . . . . . . . . . 29 9.3.2 Interrupt flags/masks registers . . . . . . . . . . . . 29 9.3.3 Video input processing control registers. . . . . 30 9.3.4 Color space conversion registers . . . . . . . . . . 34 9.3.5 Video format registers. . . . . . . . . . . . . . . . . . . 36 9.3.6 HDMI video formatter control registers . . . . . . 40 9.3.7 Timer control registers . . . . . . . . . . . . . . . . . . 42 9.3.8 9.3.9 9.3.10 9.4 9.4.1 9.4.2 9.4.3 9.5 9.5.1 9.5.2 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.7 9.7.1 9.7.2 9.7.3 9.7.4 9.8 9.8.1 9.8.2 10 11 12 13 13.1 13.2 13.3 14 15 16 16.1 16.2 16.3 16.4 17 18 NDIV register . . . . . . . . . . . . . . . . . . . . . . . . . 42 Control registers. . . . . . . . . . . . . . . . . . . . . . . 42 Current page address register . . . . . . . . . . . . 43 Scaler page register definitions . . . . . . . . . . . 43 Scaler control registers . . . . . . . . . . . . . . . . . 48 Scaling input time base generator control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current page address register . . . . . . . . . . . . 55 PLL settings page register definitions . . . . . . 55 PLL serial registers . . . . . . . . . . . . . . . . . . . . 57 Current page address register . . . . . . . . . . . . 63 Information frames and packets page register definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Vendor-specific InfoFrame registers. . . . . . . . 70 Auxiliary video information InfoFrame registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Source product description InfoFrame registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Audio InfoFrame registers . . . . . . . . . . . . . . . 76 MPEG source InfoFrame registers . . . . . . . . . 79 Current page address register . . . . . . . . . . . . 81 Audio settings and content info packets page register definitions . . . . . . . . . . . . . . . . . . . . . 81 Audio input processor control registers . . . . . 87 ISRC packets registers. . . . . . . . . . . . . . . . . . 91 Audio content protection packet registers . . . 94 Current page address register . . . . . . . . . . . . 98 HDMI and DVI page register definitions . . . . . 98 HDMI control registers . . . . . . . . . . . . . . . . . 100 Current page address register . . . . . . . . . . . 100 Limiting values . . . . . . . . . . . . . . . . . . . . . . . 100 Thermal characteristics . . . . . . . . . . . . . . . . 100 Static characteristics . . . . . . . . . . . . . . . . . . 101 Dynamic characteristics . . . . . . . . . . . . . . . . 103 Input format . . . . . . . . . . . . . . . . . . . . . . . . . 104 Example of supported video . . . . . . . . . . . . 105 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . 107 Application information . . . . . . . . . . . . . . . . 110 Package outline . . . . . . . . . . . . . . . . . . . . . . . 111 Soldering of SMD packages . . . . . . . . . . . . . 112 Introduction to soldering. . . . . . . . . . . . . . . . 112 Wave and reflow soldering . . . . . . . . . . . . . . 112 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . 112 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . 113 Soldering: additional information . . . . . . . . 114 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 114
continued >>
TDA9983B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 20 May 2008
118 of 119
NXP Semiconductors
TDA9983B
150 MHz pixel rate HDMI transmitter
116 117 117 117 117 117 117 118
19 20 20.1 20.2 20.3 20.4 21 22
Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 May 2008 Document identifier: TDA9983B_1

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